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1. 发明专利

JP2010093207A Wiring structure for solder bond inspection of printed circuit board 有权
标题翻译：印刷电路板焊接检查接线结构
公开(公告)号：JP2010093207A
公开(公告)日：2010-04-22
申请号：JP2008264429
申请日：2008-10-10
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIMAZAKI MUTSUMI , KANETANI MASAO
IPC分类号： H05K3/34 , H05K1/11
摘要： PROBLEM TO BE SOLVED: To obtain a wiring structure for solder bond inspection which achieves the measurement of impedance difference according to the bonded state of a solder bond portion using TDR, in a printed circuit board having the solder bond portion.
SOLUTION: The printed circuit board includes transmission lines 4, 7 of transmission delay time Ls, which connect between pads 2, 5 to which a terminal for power feeding of electronic components to be mounted is solder-bonded and power feeding layers 3, 6, test pads 8, 9 arranged in the position where the transmission delay time from the pads on the transmission lines is Lt (Lt≤Ls/2). When the test pads 8, 9 are arranged apart from the transmission lines 4, 7, between the test pads 8, 9 and the transmission lines 4, 7 is connected through branch transmission lines 10, 11 whose transmission delay time is a (a≤Ls-Lt).
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在具有焊料接合部分的印刷电路板中，获得焊接接合检查的接线结构，其实现使用TDR的焊接接合部分的接合状态下的阻抗差的测量。
解决方案：印刷电路板包括传输延迟时间Ls的传输线路4,7，其连接在焊盘2,5之间，用于供电的电子部件的端子焊接到其上并且馈电层3 ，6，布置在从传输线上的焊盘的传输延迟时间为Lt（Lt≤Ls/ 2）的位置的测试焊盘8,9。当测试焊盘8,9与传输线路4,7分开时，测试焊盘8,9与传输线路4,7之间的传输延迟时间为（a≤ LS-LT）。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2011139229A Electronic apparatus 有权
标题翻译：电子设备
公开(公告)号：JP2011139229A
公开(公告)日：2011-07-14
申请号：JP2009297137
申请日：2009-12-28
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YOSHIHARA YUKITERU , NISHI SHINYA , YOSHIOKA KENGO , KOYAMA MASATO , SHIMAZAKI MUTSUMI
IPC分类号： H03H7/075
摘要： PROBLEM TO BE SOLVED: To significantly suppress EMI by suppressing a common mode current that occurs inside an electronic apparatus. SOLUTION: A current phase adjusting function section 101 for coping with EMI is provided back and forth of case lead-in ports (power source wiring connection portions 102a and 102b) for: power source wirings 103a, 104a and 104c led from an external power source to supply power to a main circuit 105 in a case; and ground wirings 103b, 104b and 104d. The current phase adjusting function section 101 has a circuit configuration including a capacitor C1 and inductors L1 and L2 which allows a phase difference between the current flowing on the power supply wiring 104a and the ground wiring 104b near the case lead-in ports to be set 180° by a common mode voltage of the power source wirings 103a, 104a and 104c and the ground wirings 103b, 104b and 104d. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：通过抑制在电子设备内发生的共模电流来显着抑制EMI。解决方案：用于应对EMI的电流相位调节功能部分101来自壳体引入端口（电源布线连接部分102a和102b）的前后提供：用于从电源线布线103a，104a和104c引出的电源布线连接部分外部电源，用于向壳体内的主电路105供电; 和接地布线103b，104b和104d。电流相位调整功能部101具有包括电容器C1和电感器L1，L2的电路结构，该电容器C1和电感器L1允许流过电源线104a的电流与外壳引入口附近的接地布线104b之间的相位差被设定电源配线103a，104a，104c和接地配线103b，104b，104d的共模电压为180°。版权所有（C）2011，JPO＆INPIT

3. 发明专利

JP2009250761A Substrate connection inspection apparatus 审中-公开
标题翻译：基板连接检查装置
公开(公告)号：JP2009250761A
公开(公告)日：2009-10-29
申请号：JP2008098335
申请日：2008-04-04
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KANETANI MASAO , SHIMAZAKI MUTSUMI , ISHII HIROYUKI
IPC分类号： G01R31/02 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a substrate connection inspection apparatus for inspecting in a short time connections between a semiconductor device and a mounting substrate mounted with the semiconductor device, and for detecting a defective article.
SOLUTION: The substrate connection inspection apparatus 1 includes a probe section 7 wherein probes 8 are arranged, an interface substrate 5, a TDR measuring instrument 10, and a personal computer 15. The plurality of probes 8 are simultaneously brought into contact with a plurality of lands 4 provided on the printed substrate 2 mounted with the semiconductor device 50. Along with inputting pulses generated in the TDR measuring instrument 10 from the probes to the lands, reflected waves reflected after being input are measured.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于在半导体器件和安装有半导体器件的安装基板之间的短时间连接中检查并检测缺陷物品的基板连接检查装置。＆lt; P＆gt;解决方案：基板连接检查装置1包括其中布置有探针8的探针部分7，界面基底5，TDR测量仪器10和个人计算机15.多个探针8同时与设置在安装有半导体器件50的印刷基板2上的多个焊盘4.除了在TDR测量仪器10中从探针到焊盘输入脉冲之外，还测量在输入之后反射的反射波。版权所有（C）2010，JPO＆INPIT

4. 发明专利

JP2008089536A Connection inspection apparatus for integrated circuit device 审中-公开
标题翻译：集成电路设备连接检查装置
公开(公告)号：JP2008089536A
公开(公告)日：2008-04-17
申请号：JP2006273723
申请日：2006-10-05
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KANETANI MASAO , SHIMAZAKI MUTSUMI
IPC分类号： G01R31/02 , G01R1/067 , G01R31/28
摘要： PROBLEM TO BE SOLVED: To construct a connection inspection apparatus for integrated circuit devices capable of checking the quality of coupling sections of integrated circuit devices with a high degree of accuracy in a short time.
SOLUTION: The connection inspection apparatus for integrated circuit devices is constructed of a multipoint probe equipped with a test wave application circuit, where a plurality of probe pins contacting a plurality of contacting parts of an inspected integrated circuit device, respectively, are implanted in an insulating plate, connected to a test wave application terminal applying test wave through switching elements for each probe pin, a switching control means outputting switch signal selectively for each one element to switching elements of the test wave application circuit to form the test wave application circuit, a test wave application means applying test wave to the test wave application circuit formed by the switching control means, and a connectedness diagnostic means observing the applied test wave and the reflected wave reflected from the inspected integrated circuit device to diagnose connectedness of the inspected integrated circuit device.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：构建能够在短时间内以高精度检查集成电路装置的耦合部分的质量的集成电路装置的连接检查装置。解决方案：用于集成电路器件的连接检查装置由配备有测试波施加电路的多点探头构成，其中分别与检测的集成电路器件的多个接触部分相接触的多个探针插入在连接到测试波施加端子的测试波施加端子上的绝缘板连接到通过每个探针的开关元件施加测试波的开关控制装置，用于选择性地将每个元件的开关信号输出到测试波施加电路的开关元件以形成测试波应用测试波应用意味着将测试波应用于由切换控制装置形成的测试波应用电路，以及连接诊断装置，观察所应用的测试波和从检查的集成电路器件反射的反射波，以诊断被检查的连接性集成电路器件。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2004287738A Transmission wave form analyzing device 有权
公开(公告)号：JP2004287738A
公开(公告)日：2004-10-14
申请号：JP2003077797
申请日：2003-03-20
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIMAZAKI MUTSUMI , YAMANAKA YASUHIRO , KUSANO YOSHIYUKI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To automatically execute the prediction of any influence on circuit parts due to signal deterioration in a transmission circuit for executing the high speed serial transmission of digital signals.
SOLUTION: As for a transmission circuit to be analyzed in circuit descriptions prepared by a simulation circuit description generating part 5, a repeated analysis control part 6 designates circuit parts to be replaced with an ideal transmission path model to a model replacing part 7, and designates the analysis of transmission waveform in a status that the ideal transmission path model replaced by the model replacing part 7 is included to a transition analyzing part 8a by repeatedly executing the above designation processing the same number of times as the number of the circuit parts. A deterioration parameter measuring part 12 measures a deterioration parameter being a signal deterioration index from the analytic result of the transmission waveform obtained for each of those circuit parts replaced with the ideal transmission path model as to the transmission circuit to be analyzed.
COPYRIGHT: (C)2005,JPO&NCIPI

6. 发明专利

JP2004272436A Method for creating equivalent circuit model of multi-pin component 审中-公开
公开(公告)号：JP2004272436A
公开(公告)日：2004-09-30
申请号：JP2003059844
申请日：2003-03-06
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KUSANO YOSHIYUKI , YAMANAKA YASUHIRO , SHIMAZAKI MUTSUMI
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To create a contracted model by freely cutting out an equivalent circuit part necessary for analysis from an entire equivalent circuit model of multi-pin component.
SOLUTION: An entire equivalent circuit model description file of multi-pin component created so that the correlation with a pin name related to every element is found (ST1 and 2). A pin name used for analysis in the entire equivalent circuit model description file is designated to extract an equivalent circuit part of an object of analysis (ST 3 and 4), and an electric coupling value of the pin used for analysis with peripheral pins is set (ST5). The set electric coupling value is used as a reference value to extract the equivalent circuit part of a peripheral pin having a strong electric coupling with the pin used for analysis (ST 6 and 7), and the equivalent circuit part of the peripheral pin is added to the equivalent circuit part of the object of analysis to create an equivalent circuit model description file (ST 8).
COPYRIGHT: (C)2004,JPO&NCIPI

7. 发明专利

JP2012189396A Ic chip, semiconductor component, test probe, handy multi-tester, and communication device 审中-公开
标题翻译： IC芯片，半导体元件，测试探头，手持式多功能测试仪和通讯设备
公开(公告)号：JP2012189396A
公开(公告)日：2012-10-04
申请号：JP2011052101
申请日：2011-03-09
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIMAZAKI MUTSUMI , KUSANO YOSHIYUKI
IPC分类号： G01R31/28
摘要： PROBLEM TO BE SOLVED: To provide an IC chip allowing a TDR test in a low-cost configuration.SOLUTION: An IC chip for a TDR (Time Domain Reflectometry) test comprises: a clock generation part for generating a clock signal; a pulse generation part for generating a pulse using the clock signal as a trigger and outputting it to a test target; a multiplication part for multiplying the clock signal to generate a multiplied clock signal; an A/D converter for performing an A/D conversion of a reflection signal from the test target in synchronization with the multiplied clock signal and sampling it as reflection data; a memory for storing the sampled reflection data; and a communication control part for receiving a readout command from the outside and outputting the reflection data stored in the memory to the outside according to the readout command.
摘要翻译：要解决的问题：提供允许以低成本配置进行TDR测试的IC芯片。解决方案：用于TDR（时域反射仪）测试的IC芯片包括：时钟产生部分，用于产生时钟信号; 脉冲发生部，用于使用所述时钟信号作为触发来产生脉冲，并将其输出到测试对象; 乘法部分，用于乘以时钟信号以产生相乘的时钟信号; A / D转换器，用于与倍增时钟信号同步地执行来自测试对象的反射信号的A / D转换，并将其作为反射数据进行采样; 用于存储采样的反射数据的存储器; 以及通信控制部分，用于从外部接收读出命令，并根据读出命令将存储在存储器中的反射数据输出到外部。版权所有（C）2013，JPO＆INPIT

8. 发明专利

JP2005346613A Device and program for generating input data for simulator 审中-公开
标题翻译：用于生成模拟器的输入数据的设备和程序
公开(公告)号：JP2005346613A
公开(公告)日：2005-12-15
申请号：JP2004168295
申请日：2004-06-07
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIMAZAKI MUTSUMI , KUSANO YOSHIYUKI
IPC分类号： G06F17/50 , G06F19/00
摘要： PROBLEM TO BE SOLVED: To provide a simulator input data generation device which quickly generates input data by which a calculation result with a smaller error is obtained when simulation is performed by a circuit simulator. SOLUTION: A logical data pattern generation section 3 generates a logical data pattern constituted by combination of 0 and 1. A PWL function table generation section 5 generates input data for a simulator by using the logical data pattern which is generated by the logical data pattern generation section 3. A signal setup condition management section 2 memorizes a format according to a type of a simulator as a format type for simulator input data which is generated by the logical data pattern generation section 3. A SPICE description output section 6 sets up the format of simulator input data generated by the PWL function table generation section 5 to output to a SPICE file 25 based on the format type memorized by the signal setups condition management section 2. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种模拟器输入数据生成装置，其在通过电路模拟器执行仿真时，快速生成输入数据，通过该输入数据获得具有较小误差的计算结果。解决方案：逻辑数据模式生成部分3生成由0和1的组合构成的逻辑数据模式.PWL功能表生成部分5通过使用逻辑数据模式生成的逻辑数据模式来生成模拟器的输入数据数据模式生成部3.信号设定条件管理部2存储根据模拟器的类型的格式，作为由逻辑数据模式生成部3生成的模拟器输入数据的格式.SPICE描述输出部6设定根据由信号设置条件管理部分2存储的格式类型，提取由PWL功能表生成部分5生成的模拟器输入数据的格式，输出到SPICE文件25中。（C）2006，JPO＆NCIPI

9. 发明专利

JP2009111138A Semiconductor integrated circuit package and circuit substrate 审中-公开
标题翻译：半导体集成电路封装和电路基板
公开(公告)号：JP2009111138A
公开(公告)日：2009-05-21
申请号：JP2007281550
申请日：2007-10-30
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIMAZAKI MUTSUMI
IPC分类号： H01L23/12 , H01L25/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit package which can arrange a bypass capacitor mounted on the rear surface of a circuit substrate not to deviate from a power feeding current path to a semiconductor integrated circuit in a package.
SOLUTION: All of power supply terminals (VCC pins 4) which supply power to the semiconductor integrated circuit that is sealed up and bump electrodes 2 used as ground potential terminals (GND pins 5) are contained in a bump electrode array arranged from around the center toward outside in four directions, in crisscross manner, in the arrangement region of the bump electrodes 2 that are external connection terminals. In the circuit substrate, via holes, to which the bump electrodes 2 used as power supply terminals (VCC pins 4) and ground potential terminals (GND pins 5) are connected, align along the crisscross space assured for arranging bypass capacitors on the rear surface of substrate. So the bypass capacitors are arranged not to deviate from a feeding current path to the semiconductor integrated circuit in a package.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体集成电路封装，其能够将安装在电路基板的背面上的旁路电容器布置成不偏离馈送电流路径到封装中的半导体集成电路。
解决方案：为封闭的半导体集成电路提供电源的所有电源端子（VCC引脚4）和用作接地电位端子（GND引脚5）的凸起电极2都包含在从在作为外部连接端子的凸块电极2的布置区域中，以四边形方向在四个方向上围绕中心朝向外侧。在电路基板中，连接作为电源端子（VCC引脚4）的突起电极2和接地电位端子（GND引脚5）的通孔与沿着在后表面配置旁路电容器的保证的十字形空间对齐的底物。因此，旁路电容器被布置成不偏离馈送电流路径到封装中的半导体集成电路。版权所有（C）2009，JPO＆INPIT

10. 发明专利

JP2007107905A Logical circuit for evaluating substrate power supply, and substrate power supply evaluation method 审中-公开
标题翻译：用于评估基板电源的逻辑电路和基板电源评估方法
公开(公告)号：JP2007107905A
公开(公告)日：2007-04-26
申请号：JP2005296198
申请日：2005-10-11
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KUSANO YOSHIYUKI , SHIMAZAKI MUTSUMI , HORIKOSHI MIKA , YAMANAKA YASUHIRO , SAKAI HIROAKI
IPC分类号： G01R31/28
CPC分类号： G01R31/2846 , G01R31/31721
摘要： PROBLEM TO BE SOLVED: To provide a logical circuit for evaluating substrate power supply and substrate power supply evaluation method, capable of evaluating anti power supply noise and cut and divide the defective part at the time of occurrence of malfunction. SOLUTION: A logic circuit 1 for substrate power supply for evaluation for assembling into the logic element device mounted on the product substrate is provided with: a circuit 2 for simulating the action of the logic element device with an arbitrary frequency to the usage rate variable using the prescribed circuit among the usable all logic element devices; a circuit 3 for determining the normal/abnormal of the circuit 2; a circuit 4 for setting a using rate when the operation stop is indicate to the circuit 2 by controlling the execution of the circuit 2 based on the result of the determination of the circuit 3; and a circuit 5 for outputting the result of the determination of the circuit 3 and the usage rate set by the circuit 4 externally. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于评估基板电源和基板电源评估方法的逻辑电路，其能够评估反电源噪声并且在故障发生时对缺陷部分进行分割。解决方案：用于评估组装到安装在产品基板上的逻辑元件装置的基板电源的逻辑电路1具有：电路2，用于模拟具有任意频率的逻辑元件装置的动作到使用在可用的所有逻辑元件装置中使用规定电路的速率变量; 用于确定电路2的正常/异常的电路3; 电路4，用于通过基于电路3的确定结果控制电路2的执行，将操作停止时的使用率设定为电路2; 以及用于输出电路3的确定结果和由电路4设置的使用率的电路5。版权所有（C）2007，JPO＆INPIT

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