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1. 发明专利

JP2010124292A Communication apparatus and communication system 有权
标题翻译：通信设备和通信系统
公开(公告)号：JP2010124292A
公开(公告)日：2010-06-03
申请号：JP2008296613
申请日：2008-11-20
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MINAMI KENJI , MAEDA YASUO , ANDO SHIGEO , MANABE KATSUSHIGE
IPC分类号： H04W28/00 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To improve throughput of data communication by specifying a transmission frame of a control message between apparatuses and simplifying packaging of error processing in a communication apparatus that performs scheduling of data channels in a frame having a fixed frame length.
SOLUTION: In the communication apparatus, a creating section of a data creation request 300 creates a band request for allocating into a data channel a transmission time of a control message created by a control message creating section 340 and of generated user data. A receiving section of a data transmission request 310 receives the band request transmitted from the creating section of a data creation request 300, and a scheduler section 320 creates a schedule by allocating a band into the data channel. At such a time, a response message to the request message is allocated to a frame next to the frame to which the request message has been allocated.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：通过在设备之间指定控制消息的传输帧并简化在具有固定帧长的帧中执行数据信道的调度的通信设备中的错误处理的打包来提高数据通信的吞吐量。解决方案：在通信装置中，数据创建请求300的创建部分创建用于向数据信道分配由控制消息创建部分340创建的控制消息的传输时间和生成的用户数据的频带请求。数据发送请求310的接收部分接收从数据创建请求300的创建部分发送的频带请求，并且调度器部分320通过将频带分配到数据信道中来创建调度。在这样的时间，向请求消息的响应消息被分配给已经分配了请求消息的帧的旁边的帧。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2005175717A Video data distribution apparatus 审中-公开
标题翻译：视频数据分配设备
公开(公告)号：JP2005175717A
公开(公告)日：2005-06-30
申请号：JP2003410860
申请日：2003-12-09
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MANABE KATSUSHIGE
IPC分类号： H04N7/18 , H04N7/173 , H04N19/00 , H04N19/115 , H04N19/146 , H04N19/196 , H04N19/423 , H04N19/70 , H04N21/2187 , H04N21/231 , H04N21/61 , H04N7/24
摘要： PROBLEM TO BE SOLVED: To sequentially store coded data the amount of which is not constant so as to distribute the stored video image and distribute newest coded data as a live video image in response to a request from a terminal.
SOLUTION: A video data distribution apparatus includes: a rate control section 104 for setting the coding rate of a coding section 103 on the basis of distribution state information; a fluctuation absorbing buffer 106 for absorbing the fluctuation of the amount of coded data and attaching storage time to the data; a coded data reception section 105 for receiving the coded data, writing the received data to the fluctuation absorbing buffer 106 and transmitting a live video image to a live distribution control section 110 upon a request for the live video image distribution from the terminal; a storage management section 107 for sequentially storing the coded data written in the fluctuation absorbing buffer 106 to a storage area 108 and transmitting the coded data of a designated time to a storage distribution control section 109 as a stored video image in response to the request from the terminal; and a distribution section 111 for distributing the live video image or the stored video image to a network in response to the request from the terminal.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了顺序地存储其数量不恒定的编码数据，以便分配存储的视频图像，并且响应于来自终端的请求，将最新的编码数据分发为实时视频图像。视频数据分配装置包括：速率控制部分104，用于根据分配状态信息设置编码部分103的编码率; 波动吸收缓冲器106，用于吸收编码数据量的波动并将存储时间附加到数据; 用于接收编码数据的编码数据接收部分105，将接收到的数据写入波动吸收缓冲器106，并且根据来自终端的直播视频图像分发请求，将实况视频图像发送到实时分发控制部分110; 存储管理部分107，用于将存储在波动吸收缓冲器106中的编码数据顺序地存储到存储区域108，并响应于来自的请求，将指定时间的编码数据发送到存储分配控制部分109作为存储的视频图像终点站; 以及分配部111，用于响应于来自终端的请求将实况视频图像或存储的视频图像分发到网络。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2009201024A Communication apparatus 有权
标题翻译：通讯设备
公开(公告)号：JP2009201024A
公开(公告)日：2009-09-03
申请号：JP2008043001
申请日：2008-02-25
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MINAMI KENJI , MAEDA YASUO , ANDO SHIGEO , MANABE KATSUSHIGE , MATSUMOTO SOICHIRO
IPC分类号： H04W72/12 , H04W72/04 , H04W74/04 , H04W84/12 , H04W84/20
摘要： PROBLEM TO BE SOLVED: To achieve efficient communications by reducing transmission delay as further as possible in a communication apparatus that performs scheduling of data channels within a frame having a fixed frame length.
SOLUTION: A time control unit 330 generates interruption processing for starting scheduling processing at a processing starting time, that is an arbitrary time during a frame cycle, predetermined in accordance with a data mount and an input time of data inputted within a cycle of one frame. In response to generation of interruption processing, a data creation request creation unit 300 creates and transmits a band request requesting assignment of bands of a data transmission time within a data channel. When a data transmission request accepting unit 310 receives the band request transmitted from the data creation request creation unit 300, a scheduler unit 320 assigns a requested band into the data channel to create a schedule.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：通过在具有固定帧长度的帧内执行数据信道的调度的通信装置中尽可能地进一步减少传输延迟来实现有效的通信。解决方案：时间控制单元330产生用于在处理开始时间开始调度处理的中断处理，该处理开始时间是在帧周期期间的任意时间，其根据数据安装预定，以及在一个周期内输入的数据的输入时间一帧。响应于中断处理的产生，数据创建请求创建单元300创建并发送请求在数据信道内分配数据传输时间的频带的频带请求。当数据发送请求接收单元310接收到从数据创建请求创建单元300发送的频带请求时，调度器单元320将所请求的频带分配给数据信道以创建调度。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2011114798A Data communication apparatus and data communication method 审中-公开
标题翻译：数据通信设备和数据通信方法
公开(公告)号：JP2011114798A
公开(公告)日：2011-06-09
申请号：JP2009271823
申请日：2009-11-30
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MANABE KATSUSHIGE
IPC分类号： H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a data communication apparatus capable of reducing delay time of relay operation.
SOLUTION: A plurality of REPs (repeaters) 20, 30, 40 are connected in series to a Master (master station) 10 in a time-division multiple access scheme, while Slaves (slave stations) 11 to 42 are connected to corresponding REPs in the time-division multiple access scheme, to relay data transmitted and received between Master 10 and Slaves 11 to 42. REPs 20, 30, 40 operate as master stations to Slaves respectively connected to themselves in the time-division multiple access scheme. When a REP operates as a master station, Master 10, or REPs 20, 30, or 40 is made to operate as a slave station of the REP, wherein the REP is directly subordinate to themselves, and thereby, data can be transmitted from the REP in operation to the Master or a REP which serves as a slave station. Since the data transmission to the upstream Master or REP is possible without waiting until the upstream Master or REP operates as a master station, delay time for the relay operation can be reduced.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供能够减少中继操作的延迟时间的数据通信装置。解决方案：多个REP（中继器）20,30,40以时分多址方式与主（主站）10串联连接，而从站（从站）11至42连接到在时分多址方案中对应的REP，用于中继在主机10和从机11至42之间发送和接收的数据.R REP 20,30,40作为主站分别作为主站分别以分时多址方案连接到它们自己的从属。当REP作为主站时，Master 10或REP 20,30或40作为REP的从站进行操作，其中REP直接从属于自己，从而可以从 REP操作给Master或作为从站的REP。由于上游主站或者REP的数据传输是可能的，而是等待上游主站或者作为主站的主站才能进行，所以可以减少中继操作的延迟时间。版权所有（C）2011，JPO＆INPIT

5. 发明专利

JPH07319797A SYSTEM CONSTITUTION RECOGNIZING METHOD 失效
公开(公告)号：JPH07319797A
公开(公告)日：1995-12-08
申请号：JP11308094
申请日：1994-05-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAKANO SHINICHI , MANABE KATSUSHIGE
IPC分类号： G06F13/12 , G06F13/14
摘要： PURPOSE:To easily automatically recognize the system constitution even with respect to an input/output controller having plural functions and to surely automatically recognize the system constitution even with respect to plural connected peripheral devices. CONSTITUTION:In an input/output controller 10, channels 11-00 and 11-0X correspond to input/output control circuits 12-00 and 12-0X respectively[, and peripheral devices are connected to input/output control circuits 12-00 and 12-0X, and channel information indicating the number of channels, connection states of peripheral devices, etc., is stored in a channel information storage circuit 13. A CPU 1a reads out channel information from the channel information storage circuit 13 to recognize the system constitution.

6. 发明专利

JP2003256226A FIRMWARE EXCHANGING DEVICE 审中-公开
公开(公告)号：JP2003256226A
公开(公告)日：2003-09-10
申请号：JP2002050788
申请日：2002-02-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： MANABE KATSUSHIGE
IPC分类号： G06F11/14 , G06F9/445 , G06F11/00
摘要： PROBLEM TO BE SOLVED: To provide an F/W exchanging device capable of exchanging the F/W of integrated equipment set in a remote place without mounting any special H/W. SOLUTION: This device is provided with an on-line F/W 20 set in integrated equipment for controlling the integrated equipment itself, an off-line F/W 30 for exchanging the on-line F/W 20, and a boot F/W 40 for starting each F/W 20 and 30, and also this device is provided with an F/W start table 17 for registering a value for making the boot F/W 40 judge the legality of exchange processing at the time of exchanging the on-line F/W 20. COPYRIGHT: (C)2003,JPO

7. 发明专利

JPH11259332A COMPUTER SYSTEM DEVICE 失效
公开(公告)号：JPH11259332A
公开(公告)日：1999-09-24
申请号：JP6013898
申请日：1998-03-11
申请人： MITSUBISHI ELECTRIC CORP
发明人： MANABE KATSUSHIGE
IPC分类号： G06F11/22 , G06F1/24
摘要： PROBLEM TO BE SOLVED: To improve availability by continuing operation while performing degenerated operation as a whole device even when one part of hardware fails and to attain improvement in maintainability by storing abnormality information. SOLUTION: Based on an initializing processing program 12a, a microprocessor 11 initializes input/output control circuits 15a and 15b. When any abnormality is detected, that input/output control circuit and the abnormality information corresponding to the input/output control circuit are stored in an abnormality information table 13a of a memory 13, and when at least a hardware for operating an operating system(OS) is normal, the move to the OS is performed by continuing the initialization as it is.

8. 发明专利

JPH08335200A INPUT/OUTPUT CONTROLLER AND COMPUTER SYSTEM DEVICE 失效
公开(公告)号：JPH08335200A
公开(公告)日：1996-12-17
申请号：JP13975195
申请日：1995-06-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAKANO SHINICHI , MANABE KATSUSHIGE
IPC分类号： G06F13/10 , G06F13/12
摘要： PURPOSE: To provide an input/output controller and a computer system device by means of which the function and state of input/output control can be easily and flexibly changed. CONSTITUTION: This input/output controller is provided with a ROM 13 storing the microprogram of a microprocessor 10, input/output control circuit 1 for connecting input/output devices 17 and 18 under the control of the microprocessor 10, dip switch 15 for setting an operation change mode concerning input/output control, flash EEPROM 12 having a program setting table 12a and a hardware setting table 12b, and monitor control part 14 for controlling the data reloading of respective tables due to a monitoring device 16 in the operation change mode.

9. 发明专利

JP2001014256A COMPUTER SYSTEM HAVING SHARED DISK DEVICE 失效
公开(公告)号：JP2001014256A
公开(公告)日：2001-01-19
申请号：JP18516699
申请日：1999-06-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： NAKANO SHINICHI , MANABE KATSUSHIGE , ISHIZAWA MASAYOSHI
IPC分类号： G06F13/10 , G06F3/06 , G06F13/14 , G06F15/167 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To provide an inexpensive shared disk device connecting a plurality of computers by using a SCSI bus without using a special interface. SOLUTION: A master system computer 1 and a slave system computer 2 are connected to a shared disk device 3 by a SCSI bus 4. The computer 1 issues a SCSI command to a device managing device 32 in a fixed interval, and the device 32 monitors the state of the disk device 3 by returning the state of a device abnormality outputting part 33 as a response.

10. 发明专利

JPH10289149A MEMORY ACCESS DEVICE 失效
公开(公告)号：JPH10289149A
公开(公告)日：1998-10-27
申请号：JP9417697
申请日：1997-04-11
申请人： MITSUBISHI ELECTRIC CORP
发明人： SADAYUKI KENTARO , KAWAHARA NAOHISA , MANABE KATSUSHIGE
IPC分类号： G06F12/02
摘要： PROBLEM TO BE SOLVED: To evade such a case where the overhead of software is increased to cause the increase of the processing time by transferring a program to a fast accessible RAM from a ROM when a CPU executes the program. SOLUTION: When a program access request signal, etc., is outputted from a CPU 21, the program data stored in the access addresses of an address register 25 are outputted via the ROM 28 to 30. Then the access addresses of the register 25 are increased for each output of the program data. Then the CPU 21 executes the programs stored in the ROM 28 to 30. In this case, however, the programs stored in the ROM 28 to 30 are transferred to a fast accessible RAM 33 in order to increase the program access speed when the CPU 21 actually executes the programs. Thus, the programs are executed via the accessing of the RAM 33.

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