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1. 发明专利

JPS59121605A CONTROL DEVICE OF MAGNETIC TAPE 失效
公开(公告)号：JPS59121605A
公开(公告)日：1984-07-13
申请号：JP22976382
申请日：1982-12-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIRATANI TAKAHIRO
IPC分类号： G11B20/10 , G11B5/09
摘要： PURPOSE:To decrease the number of parts and to improve reliability by constituting a control circuit of a CPU and a storage circuit which stores the program thereof, and performing data exchange and processing with the module stored on a magnetic tape. CONSTITUTION:All the operation of a control circuit (CPU11) are programmed in a storage circuit 12 and the circuit 11 executes the control procedures stored preliminarily therein. The circuit 11 outputs first the starting sequence of a module 4 stored on a magnetic tape to a data bus 13. A magnetic tape input and output circuit 2 makes said sequence into a magnetic tape input and output signal 3 and outputs a control signal for starting to the module 4. The control circuit 11 takes therein the data from a data storage circuit 7 assigned through the bus 13 and converts the same into the storage data format of the module 4 and thereafter said circuit outputs the format to the bus 13 and the storage data made as the signal 3 in the circuit 2 is outputted to the module 4.

2. 发明专利

JPH0247946A SERIAL DATA TRANSFER SYSTEM 失效
公开(公告)号：JPH0247946A
公开(公告)日：1990-02-16
申请号：JP19913388
申请日：1988-08-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIRATANI TAKAHIRO
IPC分类号： H04L12/40
摘要： PURPOSE:To reduce number of signal lines corresponding to the system change flexibly and to simplify the system constitution by setting a transfer start address, number of transmission times, a reception address and reception number to each unit and opening a serial data bus to each unit corresponding to the address so as to attain data communication between the units. CONSTITUTION:A unit No is set in advance to units 21-2n-1 of the serial transfer system by using a switch SW or the like. A control unit 1 outputs a synchronizing signal 3 to start the serial data transmission and a transfer timing 4 giving a data transfer timing to the units 21-2n-1. A section address is given from the signal 3 sequentially in the timing 4 and the units 21-2n, and the unit 1 input/output the data on a serial data bus 5 based on the bus operating permission of the units 21-2n-1 between addresses. The unit 1 outputs the transfer start address, transfer number, the reception start address and reception number at first for each of the units 21-2n-1.

3. 发明专利

JPS61182580A SWEEP DATA PROCESSOR 失效
公开(公告)号：JPS61182580A
公开(公告)日：1986-08-15
申请号：JP2183185
申请日：1985-02-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： IWASAKI TAKUMI , SHIRATANI TAKAHIRO
IPC分类号： G01S7/28 , G01R23/173 , G01S7/292 , G06F17/40
摘要： PURPOSE:To simplify a device by providing an output register, input register, timer, data memory, program memory, and a microcontroller for executing control in accordance with the contents stored in the program memory. CONSTITUTION:The microcontroller 21 outputs tuning frequency 4 through the output register 19 in accordance with a program in the program memory 22, makes the timer 14 output a strobe signal 13, inputs input level data 5 through the input register 6, and while storing the maximum value out of quantized values in one address of the data memory 7, advances the tuning frequency up to the sweep end value. In this case, a sweep start value, the seep end value, a memory start address, quantized values, and a sweep updating time value are set up in the program of the program memory 22. Since the control circuit is constituted of the microcontroller 21 and the program, the number of arts can be reduced, the device can be simplified and the reliability can be improved.

4. 发明专利

JPS57196161A VIDEO SIGNAL PROCESSOR 失效
公开(公告)号：JPS57196161A
公开(公告)日：1982-12-02
申请号：JP8327081
申请日：1981-05-28
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIRATANI TAKAHIRO , SAITOU TAKASHI
IPC分类号： G01D7/00 , G01R13/20 , G01R13/22 , G01R23/173 , H04N5/44 , H04N17/00
摘要： PURPOSE:To achieve indication of display video signals stably while accurately separated into signals and noises by comparing with a reference data a peak hold value which is obtained in a minumum section after the digitalization of display video inputs. CONSTITUTION:Display video inputs are provided to a peak hold circuit 6 through an A-D conversion circuit 5 and data formed by the peak hold circuit 6 are compared with a reference data 8 set based on the sensitivity of a receiver with a comparator circuit 7. The results of the comparison are inputted into switching circuit 9 and based on the results, the outputs are switched over. In other words, when the peak hold data are larger than the reference data, the display video inputs are identified as video signal. The outputs of the peak hold circuit 6 are transferred to a register 10 as output data in the minimum section and stored. On the other hand, when the peak hold data is smaller than the reference data, the display video signal is identified as noise component and the A-D conversion output is stored into the register 10.

5. 发明专利

JPS5616349A SIMULTANEOUS SERIAL DATA TRANSFER UNIT 失效
公开(公告)号：JPS5616349A
公开(公告)日：1981-02-17
申请号：JP9244679
申请日：1979-07-18
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIRATANI TAKAHIRO
IPC分类号： G06F13/00 , H04L12/00
摘要： PURPOSE:To decrease the input/output data lines and thus simplify the structure of the interface to secure a high accuracy, by realizing a simultaneous serial transfer of the data through three units of periodical pulses. CONSTITUTION:Start pulse P1 generated from pulse generating circuit 23, pulse train P2 having the pulse number of maximum data length and sample pulse train P3 are sent to control circuit 8a of control block 2. At the same time, pulses P1, P2 and PP3 are sent to circuit 8a via driver circuit 18 of pulse generating circuit 10 plus receiver 19 of control circuit 8b within blocks 1a and so on. In such constitution, the input data within blocks 1a and so on can be transferred input data register file 11a in block 2. And at the same time, the output data of output data register file 12 in block 2 can be transferred into blocks 1a and so on.

6. 发明专利

JPH05324347A INTERRUPTION CONTROLLER 失效
公开(公告)号：JPH05324347A
公开(公告)日：1993-12-07
申请号：JP15584792
申请日：1992-05-21
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIRATANI TAKAHIRO
IPC分类号： G06F9/48 , G06F9/46
摘要： PURPOSE:To provide an interruption controller being capable of surely grasping time at the point of time when an interruption request input is executed without nanosecond order delay. CONSTITUTION:The controller is constituted by providing a timer 2 which can be preset and a register group 3 where the generation time of the timer 2 is stored in accordance with the interruption request input IRI from the timer 2 at the point of time when the interruption request input TRI is executed so that a control circuit 7 is permitted to output time data to a data bus DB, which is stored at the time of receiving the interruption request input IRI, when reading is executed in the interruption controller 101 after an output from an in-service register 5 to the data bus DB of a vector address by an interruption response input IRe.

7. 发明专利

JPH02131614A PULSE GENERATOR 失效
公开(公告)号：JPH02131614A
公开(公告)日：1990-05-21
申请号：JP28641188
申请日：1988-11-11
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIRATANI TAKAHIRO
IPC分类号： H03K3/78
摘要： PURPOSE:To relieve the load of an arithmetic and control circuit more and to quicken the generator more by constituting the title generator in such a way that the trailing edge of a cover pulse is generated by down-count so that a simulator signal is placed in the middle when the front edge of the simulator signal and the cover pulse is set. CONSTITUTION:A comparator 19 compares an output data of a repetitive register with a count signal 15a and outputs a simulator signal 19a when they are coincident. A comparator 20 compares an output data of a front edge register 17 with the count signal 15a and outputs a cover pulse set signal 20a when they are coincident. The cover pulse set signal is set by setting a cover pulse 23a of an F/F 23 synchronously with the reference clock 2a. The comparator 21 compares the output data of a tail edge register 18 with the count signal 15a and outputs a cover pulse reset signal 21a when they are coincident. The cover pulse 21a resets the cover pulse 23a of the F/F 23 synchronously with the reference clock 2a.

8. 发明专利

JPS6079453A MEMORY DEVICE 失效
公开(公告)号：JPS6079453A
公开(公告)日：1985-05-07
申请号：JP18817183
申请日：1983-10-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHIRATANI TAKAHIRO
IPC分类号： G06F12/06 , G06F13/16 , G06F13/42 , G06F17/16
摘要： PURPOSE:To use an inexpensive and low power consumption type memory elements and speed up writing and reading operation by writing and reading data at a rate obtained by dividing a memory cycle time into N equally. CONSTITUTION:A memory access address 8 and write data 9 are distributed to and written in two memory units 20A and 20B on the arrival of every clock signal 22 with timing signals 10A and 10B generated alternately by a control circuit 21. When reading operation is performed, the control circuit 21 outputs read gate signals 13A and 13B corresponding to the timing signals 10A and 10B with a W/R switching signal 11 to control the memory units 20A and 20B, outputting an output address 16 and output data 17. Consequently, inexpensive and low power consumption type elements are used to double the W/R speed. In this case, when N sets of memory units are used, the speed become N-fold.

9. 发明专利

JPS59144929A Controlling device of peripheral equipment 失效
标题翻译：控制外围设备的设备
公开(公告)号：JPS59144929A
公开(公告)日：1984-08-20
申请号：JP1770083
申请日：1983-02-04
申请人： Mitsubishi Electric Corp
发明人： SHIRATANI TAKAHIRO , IWASAKI TAKUMI
IPC分类号： G06F13/38 , G06F12/00 , G06F15/16 , G06F15/167 , G06F15/177
CPC分类号： G06F15/167
摘要： PURPOSE:To shorten transfer time sharply by composing a peripheral equipment controlling device of two systems, i.e. a control system consisting of a main control part and a sub-control part and a common memory system, and setting up the transfer time to nA+C when the transfer volume of the whole data is (n) blocks. CONSTITUTION:When data are to be taken out from a peripheral equipment 5, a CPU1a applies a command to a CPU2a in the sub-control part 2 transmitting/ receiving data directly to/from the peripheral equipment through I/O circuits 1e, 2e, and simultaneously connects a data bus and a control signal line in a memory 6a to a data bus 2g and a control signal line 2h in the sub-control part 2 by controlling a data bus switching circuit 6b and a control switching circuit 6c in the common data memory 6 through a control signal line 8 so that the common data memory 6 can be accessed from the CPU2a and a common data memory 7 can be also accessed from the CPU1a. The CPU2a stops sequential data by switching the common data memories 6, 7 and the CPU1a executes progressive transfer during the stop.
摘要翻译：目的：通过组合两个系统的外围设备控制设备，即由主控制部分和子控制部分和公共存储器系统组成的控制系统，缩短传输时间，并将传输时间设置为nA + C 当整个数据的传输量为（n）个块时。构成：当从外围设备5取出数据时，CPU1a通过I / O电路1e，2e向CPU2a发送/从周边设备发送/接收数据的子控制部分2，并且通过控制数据总线切换电路6b和公共端的控制切换电路6c，同时将存储器6a中的数据总线和控制信号线连接到子控制部分2中的数据总线2g和控制信号线2h 数据存储器6通过控制信号线8使得公共数据存储器6可以从CPU2a访问，并且公共数据存储器7也可以从CPU1a访问。 CPU2a通过切换公共数据存储器6,7来停止顺序数据，CPU1a在停止期间执行逐行传送。

10. 发明专利

JPS58178626A Binary code data converter 失效
标题翻译：二进制代码数据转换器
公开(公告)号：JPS58178626A
公开(公告)日：1983-10-19
申请号：JP6214282
申请日：1982-04-12
申请人： Mitsubishi Electric Corp
发明人： IWASAKI TAKUMI , SHIRATANI TAKAHIRO
IPC分类号： H03M7/12
CPC分类号： H03M7/12
摘要： PURPOSE:To convert binary code data whose bit is optionally weighted into BCD code data, by using an operation circuit in stead of an ROM. CONSTITUTION:A binary counter 4a counts up binary code data inputs at reference timing. A conversion rate setting circuit 4e sets up the conversion rate into the BCD code data corresponding to the weighting of the bit of the inputted binary code data. A rate multiplier 4b outputs a pulse having a period obtained by multiplying a reference timing period by several times in accordance with the code data conversion rate. A decimal counter 4b counts up the output of the rate multiplier 4d and enables an optional value to be added and an output register 4c reads out the counted value. A control circuit 4f starts and ends the counting of said counter simultaneously and actuates the rate multipler 4d.
摘要翻译：目的：通过使用操作电路代替ROM，将其可选择的二进制码数据转换为BCD码数据。构成：二进制计数器4a在参考时间对二进制代码数据输入进行计数。转换率设定电路4e将转换率设定为与输入的二进制码数据的位的加权相对应的BCD码数据。速率倍增器4b根据代码数据转换速率输出具有通过将基准定时周期相乘多次而获得的周期的脉冲。十进制计数器4b对速率倍增器4d的输出进行计数，并使能一个可选的值，并输出寄存器4c读出计数值。控制电路4f同时开始和结束所述计数器的计数并致动速率倍增器4d。

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