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1. 发明专利

JP2008047573A Resin-sealing semiconductor device, and manufacturing apparatus and method thereof 审中-公开
标题翻译：树脂密封半导体器件及其制造装置及其方法
公开(公告)号：JP2008047573A
公开(公告)日：2008-02-28
申请号：JP2006219069
申请日：2006-08-11
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ITO TETSUO , YOSHIDA TAKAYUKI , FUKUDA TOSHIYUKI , OCHI TAKAO
IPC分类号： H01L21/56
CPC分类号： H01L21/565 , B29C45/14655 , B29C45/2708 , B29C45/34 , H01L21/561 , H01L23/3121 , H01L24/45 , H01L24/48 , H01L24/97 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2924/20751 , H01L2924/20752 , H01L2924/20753
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing apparatus and a manufacturing method of a resin-sealing semiconductor device, which manufactures a number of resin-sealing semiconductor devices at a time, by performing sealing collectively and restraining the generation of internal voids at a resin-sealing section, and also to provide the resin-sealing semiconductor device. SOLUTION: The manufacturing apparatus of a resin-sealing semiconductor device has a mold 20 for sealing resin having a cavity of a sealing resin injection space while a substrate 2 is placed inside on which a plurality of semiconductor elements 3 are mounted. The mold 20 has a resin inlet 29a for injecting a sealing resin to the cavity, and an air outlet 30a for allowing air to escape from the cavity when injecting resin. The resin inlet 29a is provided on the ceiling surface of the cavity corresponding to each semiconductor element 3. The air outlet 30a is provided corresponding to each semiconductor element 3, so that it exists around the resin inlet 29a in a plan view in the thickness direction of the substrate 2 and the sealing resin 7. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：为了提供树脂密封半导体器件的制造装置和制造方法，其通过一起进行密封并抑制内部空隙的产生来一次制造多个树脂密封半导体器件在树脂密封部分，并且还提供树脂密封半导体器件。解决方案：树脂密封半导体器件的制造装置具有用于密封具有密封树脂注入空间的空腔的树脂的模具20，同时将衬底2放置在其中安装有多个半导体元件3的内部。模具20具有用于将密封树脂注入到空腔中的树脂入口29a和用于当注入树脂时允许空气从空腔逸出的空气出口30a。树脂入口29a设置在对应于每个半导体元件3的空腔的顶表面上。空气出口30a相应于每个半导体元件3设置，使得其在厚度方向的平面图中围绕树脂入口29a存在的基板2和密封树脂7.版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2004047949A Circuit board and semiconductor device 有权
标题翻译：电路板和半导体器件
公开(公告)号：JP2004047949A
公开(公告)日：2004-02-12
申请号：JP2003090514
申请日：2003-03-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SAKAI HIROYUKI , IKEDA YOSHITO , OTA TOSHIMICHI , INOUE KAORU , NISHII KATSUNORI , YOSHIDA TAKAYUKI
IPC分类号： H05K1/16 , H01L23/12 , H05K1/02 , H05K1/18
CPC分类号： H01L2224/16225 , H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To prevent a rapture of a resistor film by eliminating the local thermal expansion of a dielectric film caused by heat from a resistor in a circuit board having the resistor film on the dielectric film. SOLUTION: In the circuit board, a resistor film 6 and a wiring conductor film 7 are provided in direct contact on a BCB film 3 which is the dielectric film of a microstrip line. Then a recess 10 wherein the thickness of the BCB film 3 immediately under the resistor film 6 is made smaller in comparison with others is formed, and the resistor film 6 is formed on the BCB film 3 in the recess 10. Through the thinned portion, the heat of the resistor film 6 is quickly dissipated to a ground conductor film 2. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过消除由电介质膜上具有电阻膜的电路板中的电阻器的电阻引起的电介质膜的局部热膨胀来防止电阻膜的破裂。解决方案：在电路板中，电阻膜6和布线导体膜7直接接触在作为微带线的电介质膜的BCB膜3上。然后形成凹部10，其中与电阻膜6正下方的BCB膜3的厚度相比较小，并且在凹部10中的BCB膜3上形成电阻膜6.通过变薄的部分，电阻膜6的热量迅速耗散到接地导体膜2.版权所有（C）2004，JPO

3. 发明专利

JP2008270503A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008270503A
公开(公告)日：2008-11-06
申请号：JP2007111089
申请日：2007-04-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YOSHIDA TAKAYUKI , HONDO TAKUMA , FUKUDA TOSHIYUKI
IPC分类号： H01L21/3205 , H01L23/02 , H01L23/52
CPC分类号： H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of low-profile and smaller size, capable of protecting a main surface from α line coming from the rear surface side, even if a semiconductor element is thin. SOLUTION: A semiconductor device 10 comprises a semiconductor element 11 in which a circuit element 18 is formed on a main surface 11a, and a first α line shielding film 21 that covers a rear surface 11b. A sum T of a thickness T1 of the semiconductor element 11 and a thickness T1 of the first α line shielding film 21 is set larger than a flying distance R1 of α line that enters the first α line shielding film 21 and then travels toward the main surface 11a of the semiconductor element 11 along the thickness direction. Even if a mold resin and wiring are arranged to adjoin the rear surface 11b of the semiconductor element 11, and even if the α line is emitted from the metal material contained in them, it does not reach so far as the main surface 11a of the semiconductor element 11, avoiding the effect on the circuit element 18. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：即使半导体元件薄，也可以提供一种小型化，小尺寸的半导体器件，其能够保护来自背面侧的α线的主表面。解决方案：半导体器件10包括在主表面11a上形成电路元件18的半导体元件11和覆盖后表面11b的第一α线屏蔽膜21。将半导体元件11的厚度T1和第一α线屏蔽膜21的厚度T1的和T设定为大于进入第一α线屏蔽膜21的α线的飞行距离R1，然后向主体半导体元件11的厚度方向的表面11a。即使模制树脂和布线被布置成邻接半导体元件11的后表面11b，并且即使α线从包含在其中的金属材料发射，也不会达到这样的主表面11a 半导体元件11，避免对电路元件18的影响。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2008124228A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008124228A
公开(公告)日：2008-05-29
申请号：JP2006306085
申请日：2006-11-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HISHIOKA MAIKO , YOSHIDA TAKAYUKI
IPC分类号： H01L23/50
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49109 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which can have a lead frame provided with an increased number of leads easily. SOLUTION: When electrodes arranged in a zigzag form on a chip 4 mounted on an island 7 of a lead frame are electrically connected to leads 8, 9 of the lead frame by means of metallic thin lines 5, the leads 8, 9 are arranged in multiple stages or in a zigzag array, thus obtaining the lead frame having an increased number of pins with a narrow pitch. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种半导体器件，其可以容易地具有设置有更多引线数量的引线框架。解决方案：当安装在引线框架岛岛7上的以锯齿形布置的电极通过金属细线5与引线框架的引线8,9电连接时，引线8,9 被布置成多个阶段或Z字形阵列，从而获得具有较窄间距的引脚数量增加的引线框架。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2005322703A Semiconductor integrated circuit device and manufacturing method thereof 审中-公开
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：JP2005322703A
公开(公告)日：2005-11-17
申请号：JP2004137964
申请日：2004-05-07
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YOSHIDA TAKAYUKI , TSUURA KATSUHIKO
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/82
CPC分类号： H01L2224/11 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/92125 , H01L2924/14 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can obtain the desired memory characteristics, can also be matched with a high-frequency circuit as an external circuit, even when the high-density mounting requiring many terminals of the semiconductor circuit element is requested, can adjust the threshold of the semiconductor circuit element, and can prevent damage by corrosion or by impact from the outside. SOLUTION: In the semiconductor integrated circuit device, an Al electrode pad 10 is formed to be a redundant circuit, a structure covered with BCB or the like, having an electrode aperture, is formed on the Al electrode pad 10, and a conductor 11 is formed among the desired pads of a plurality of Al electrode pads 10. For the first issue, the conductor 11 of the redundant circuit forms a fuse for memory redundant relief. Accordingly, the flip-chip mounting structure, enabling redundant relief of the memory after the formation of bumps, can be realized. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供可以获得期望的存储特性的半导体集成电路器件，也可以与作为外部电路的高频电路匹配，即使当需要许多端子的高密度安装要求半导体电路元件，可以调节半导体电路元件的阈值，并且可以防止腐蚀或来自外部的冲击的损坏。解决方案：在半导体集成电路器件中，Al电极焊盘10形成为冗余电路，在Al电极焊盘10上形成具有电极孔的BCB等覆盖的结构，并且导体11形成在多个Al电极焊盘10的期望的焊盘之间。对于第一个问题，冗余电路的导体11形成用于存储器冗余浮雕的熔丝。因此，可以实现倒装芯片安装结构，能够在形成凸块之后实现对存储器的冗余的释放。版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2005079431A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2005079431A
公开(公告)日：2005-03-24
申请号：JP2003309880
申请日：2003-09-02
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MATSUMURA KAZUHIKO , YOSHIDA TAKAYUKI , MATSUMOTO KATSUYOSHI , KAINO NORIYUKI , KAWABATA TAKESHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/12
CPC分类号： H01L2224/11 , H01L2224/73204 , H01L2224/92125
摘要： PROBLEM TO BE SOLVED: To prevent the disconnection of the top layer wiring of a semiconductor chip under an electrode for external connection by the film stress of the metal film of the electrode for the external connection. SOLUTION: A semiconductor device is provided with a first organic insulation film 6, a wiring pattern 7 and a second organic insulation film 14, and is provided with the wiring or electrode 13 of a size equal to or larger than the second opening, where the electrode 5 for the external connection is formed, of the first organic insulation film 6 on the position of the top layer of the semiconductor chip 1 facing the electrode 5 for the external connection of the wiring pattern 7. Thus, damages given to the wiring of the top layer of the semiconductor chip 1 by the generation of cracks on a protective film 4 by the film stress of the metal film forming the electrode 5 for the external connection are reduced. Thus, the process cost of the semiconductor chip 1 is reduced. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止用于外部连接的电极的金属膜的膜应力，用于外部连接的电极下方的半导体芯片的顶层布线的断开。解决方案：半导体器件设置有第一有机绝缘膜6，布线图案7和第二有机绝缘膜14，并且设置有等于或大于第二开口的布线或电极13 其中形成有用于外部连接的电极5的第一有机绝缘膜6位于半导体芯片1的顶层位于布线图案7的外部连接的电极5的位置上。因此，由于形成用于外部连接的电极5的金属膜的膜应力，在保护膜4上产生裂纹导致半导体芯片1的顶层的布线减少。因此，半导体芯片1的工艺成本降低。版权所有（C）2005，JPO＆NCIPI

7. 发明专利

JP2003068780A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2003068780A
公开(公告)日：2003-03-07
申请号：JP2001260765
申请日：2001-08-30
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： NOKUBO TAKESHI , YOSHIDA TAKAYUKI , MATSUMOTO KATSUYOSHI , SHIMOISHIZAKA NOZOMI , KAWABATA TAKESHI , ISHIKAWA KAZUHIRO
IPC分类号： H01L21/60
CPC分类号： H01L2224/05553 , H01L2224/451 , H01L2224/48 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/4847 , H01L2224/49 , H01L2224/4917 , H01L2224/49171 , H01L2224/49175 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082 , H01L2924/30107 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To overcome a problem that it is impossible to transmit normal signals due to the electric signal interference between the fine metal wires because the metal wires are close to each other, in a conventional manufacturing method of a semiconductor device, especially in a multiple pin or a narrow pitch semiconductor device. SOLUTION: A fine metal wire 8 for electrically connecting an electrode 6 of a semiconductor chip to a lead part 7 of a lead frame is bonded so that adjacent fine metal wires 8 cross each other to reduce the mutual inductance and suppress generation of cross talk between signals passing the wires.
摘要翻译：要解决的问题：为了克服由于金属线彼此接近而由于金属细线之间的电信号干扰而不能传输正常信号的问题，在以往的半导体器件的制造方法中尤其如此多引脚或窄间距半导体器件。解决方案：用于将半导体芯片的电极6与引线框架的引线部分7电连接的细金属线8被接合，使得相邻的细金属丝8彼此交叉以减少互感并抑制互相之间的串扰的产生通过电线的信号。

8. 发明专利

JP2003037223A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2003037223A
公开(公告)日：2003-02-07
申请号：JP2001225935
申请日：2001-07-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SHIMOISHIZAKA NOZOMI , YOSHIDA TAKAYUKI , NOKUBO TAKESHI , ISHIKAWA KAZUHIRO , MATSUMOTO KATSUYOSHI , KAWABATA TAKESHI
IPC分类号： H01L23/34
摘要： PROBLEM TO BE SOLVED: To solve the problem of the need for forming deep unevenness of a radiation fin, in order to improve the cooling effect of a semiconductor element, because of the use of a radiation mechanism using convection with air, so that superior cooling effect is not obtained, when normally awailable silicon substrate on the market (e.g., 625-725 μm of thickness) is subjected to unevenness working.
SOLUTION: A trench 8 is formed on the rear 7 of a semiconductor element 5. Refrigerant 10, which has flowed into the trench from a refrigerant flow-in hole 11 of a retaining plate 9, passes through the trench 8 and flows out from a refrigerant flow-out hole 12 of the retaining plate 9, thereby dissipating the heat generated from the semiconductor element 5 with high efficiency.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题为了解决形成辐射翅片的深度不均匀性的问题，为了提高半导体元件的冷却效果，由于使用与空气对流的辐射机构，因此优异的冷却当市场上通常可用的硅基板（例如，625-725μm的厚度）经受不均匀加工时，不能获得效果。解决方案：在半导体元件5的后部7上形成有沟槽8.已经从保持板9的制冷剂流入孔11流入沟槽的制冷剂10通过沟槽8并从制冷剂流出孔12，从而以高效率散发由半导体元件5产生的热量。

9. 发明专利

JP2008141215A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2008141215A
公开(公告)日：2008-06-19
申请号：JP2007339218
申请日：2007-12-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SAKAI HIROYUKI , YOSHIDA TAKAYUKI , OTA TOSHIMICHI
IPC分类号： H01L23/12 , H01L21/60 , H01L25/00 , H01P1/04 , H01P5/08
CPC分类号： H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To provide a small MMIC having small parasitic effect, in which the resonance or unwanted oscillations are less apt to occur, even if flip-chip bonding is performed, and to surely carry out MMICs and MFICs mounting. SOLUTION: A GND plane 12, a dielectric film 13, and a first wiring pattern 14 are formed sequentially on the principal plane of a substrate 11 made of Si, or the like, and the first wiring pattern 14, the dielectric film 13, and the GND plane 12 constitute a micro stripline. An MMIC chip 22, whose element-forming surface has a high-frequency transistor and a second wiring pattern 21, is secured on the substrate 11 using MBB method, with the element-forming surface and the principal plane of the substrate 11 made to face each other. In an MMIC chip 22, the second wiring pattern 21, the dielectric film 13 provided on the substrate 11, and the GND plane 12 constitute the micro stripline. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：即使执行倒装芯片接合，也可以提供具有小的寄生效应的小型MMIC，其中谐振或不期望的振荡不易发生，并且可靠地执行MMIC和MFIC的安装。解决方案：在由Si等制成的基板11的主平面上依次形成GND平面12，电介质膜13和第一布线图案14，并且第一布线图案14，电介质膜 13，GND平面12构成微带线。使用MBB法将元件形成表面具有高频晶体管和第二布线图案21的MMIC芯片22固定在基板11上，使基板11的元件形成表面和主平面朝向彼此。在MMIC芯片22中，第二布线图案21，设置在基板11上的电介质膜13和GND平面12构成微带线。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2007012893A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007012893A
公开(公告)日：2007-01-18
申请号：JP2005192237
申请日：2005-06-30
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： YAGO MASATOSHI , YOSHIDA TAKAYUKI , OTANI KATSUMI , SUZUKI HIROAKI
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L2224/05554 , H01L2224/48091 , H01L2224/48227 , H01L2224/49 , H01L2224/49171 , H01L2224/49179 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To improve the reliability of a semiconductor device by preventing the occurrence of failures caused by a wiring at a corner of a mounted chip. SOLUTION: The semiconductor device is provided with a semiconductor chip 101 in which a plurality of electrodes 102 are arranged side by side to the outer periphery of the four sides; a wiring substrate 105 in which the semiconductor chip 101 is mounted on one face, and a plurality of electrodes 104 corresponding to the electrodes 102 of the semiconductor chip 101 are arranged side by side; and a wire 103 for electrically connecting the electrodes 102 of the semiconductor chip 101 with the electrodes 104 of the wiring substrate 105, respectively. The electrode arrangement at the corner part of each side of the semiconductor chip 101 is arranged at an angle of being bent to the center side of the semiconductor chip to the electrode arrangements other than those of at the corner parts. By this, it is possible to secure a clearance between wirings adjacent to each other at each corner part of the semiconductor chip. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过防止由安装的芯片的角落处的布线引起的故障的发生来提高半导体器件的可靠性。解决方案：半导体器件设置有半导体芯片101，其中多个电极102并排设置在四边的外周; 将半导体芯片101安装在一个面上的布线基板105和与半导体芯片101的电极102对应的多个电极104并列配置; 以及用于将半导体芯片101的电极102与布线基板105的电极104电连接的导线103。半导体芯片101的每一侧的角部的电极配置被配置成与半导体芯片的中心侧弯曲成与角部不同的电极配置的角度。由此，可以确保半导体芯片的每个角部处的彼此相邻的布线之间的间隙。版权所有（C）2007，JPO＆INPIT

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