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1. 发明专利

JP2008181982A Semiconductor device and reflow mounter 审中-公开
标题翻译：半导体器件和反射器
公开(公告)号：JP2008181982A
公开(公告)日：2008-08-07
申请号：JP2007013204
申请日：2007-01-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI
IPC分类号： H01L23/28
CPC分类号： H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/73265 , H01L2224/92247 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses heat load to an electronic part or a printed wiring board or the like in reflow-mounting the electronic part and easily evaluates the temperature of a solder paste so as to set the optimal temperature profile for sufficient heating of solder bonding. SOLUTION: In the resin sealed semiconductor device using a lead frame, a temperature indicating material 7 that is discolored at a specified temperature is coated to the surface of an outer lead 4b located outside the sealing resin 6 of the lead 4. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种半导体器件，其抑制对电子部件或印刷线路板等的热负载，以回流安装电子部件，并且容易地评估焊膏的温度，从而将最佳温度曲线，用于焊接焊接的充分加热。解决方案：在使用引线框架的树脂密封半导体器件中，在指定温度下变色的温度指示材料7被涂覆到位于引线4的密封树脂6外部的外引线4b的表面上。 P>版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006032580A Method of manufacturing substrate for semiconductor device 审中-公开
标题翻译：半导体器件制造衬底的方法
公开(公告)号：JP2006032580A
公开(公告)日：2006-02-02
申请号：JP2004207954
申请日：2004-07-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To manufacture the substrate for a semiconductor device in which no lead wiring for plating remains with less effects on high frequency signals.
SOLUTION: The substrate for a semiconductor device is manufactured where a semiconductor chip is mounted in which a circuit element is formed with a linear wiring 2 and a mounting terminal 3 connected to its end being formed on the surface of an insulating substrate 1. Here, a through hole 8 is formed in such arrangement as corresponding to the mounting terminal 3 and the linear wiring 2 to be plated, on an insulating sheet 6. A lead wiring 4 for plating in the direction from the mounting terminal 3 to an insulating substrate end is formed from within the through hole 8 to the surface. The insulating sheet 6 comprising the lead wiring 4 for plating is releasably jointed to the insulating substrate 1 so that the lead wiring 4 for plating connects to the mounting terminal 3. After completion of a plating process for forming a gold coating film 11 by feeding power through the lead wiring 4 for plating, the lead wiring 4 for plating is removed together with the insulating sheet 6.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了制造其中没有用于电镀的引线接线对低频信号的影响较小的半导体器件的衬底。解决方案：制造半导体器件用基板，其中安装有电路元件的半导体芯片，线形布线2和连接到其端部的安装端子3形成在绝缘基板1的表面上这里，贯通孔8形成为与安装端子3和要被电镀的线性布线2相对应的布置在绝缘片6上。用于在从安装端子3到安装端子3的方向上电镀的引线4 绝缘基板端部由通孔8内的表面形成。包括用于电镀的引线4的绝缘片6可释放地接合到绝缘基板1上，使得用于电镀的引线4连接到安装端3.在完成用于通过馈电的金涂层11的形成电镀工艺通过用于电镀的引线4，用于电镀的引线4与绝缘片6一起被去除。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2006032531A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2006032531A
公开(公告)日：2006-02-02
申请号：JP2004207089
申请日：2004-07-14
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： FURUYA KEISUKE , OTANI KATSUMI
IPC分类号： H01L21/60
摘要： PROBLEM TO BE SOLVED: To make it possible to assemble a flexible wiring board responding to the demand of high bonding accuracy in COF structure.
SOLUTION: The free region 2a of a base substrate 2 without a wiring part 4 is provided in a junction region 12 where a semiconductor chip 5 is joined to a flexible wiring board 1, and a conductor 9 composed of copper foil in a quadrangular shape is provided between inner leads 4a along the longitudinal direction of the inner leads 4a. In bonding, the base substrate 2 is exposed to high temperature so that it may be softened and spread for transformation in order to carry out eutectic fusion of a metal projection 6 and the inner leads 4a by the junction adding temperature and load. As the temperature of the junction descends to the room temperature after processing, the stress of the elasticity directed to a center arises in the free region 2a since the base substrate 2 tries to return to the original shape. Such a nonconformity point as an inner lead displacement, inner lead peeling, or the like in an assembly process is prevented by providing the conductor 9 for this stress so as to strengthen the free region 2a of the base substrate 2 so that high bonding accuracy may be made possible by inhibiting the elasticity generated in the part of this free region 2a.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：能够根据COF结构中的高粘合精度的要求来组装柔性布线板。解决方案：没有布线部分4的基底基板2的自由区域2a设置在半导体芯片5接合到柔性布线板1的接合区域12中，以及由铜箔形成的导体9 内引线4a沿着内引线4a的长度方向设置四边形。在接合时，基底基板2暴露于高温，使得其可以软化并扩展以进行变换，以便通过结加点温度和负载进行金属突起6和内引线4a的共晶熔合。随着加工温度下降到室温，由于基底基板2试图返回原来的形状，所以在自由区域2a产生弹性的应力。通过为该应力提供导体9来防止在组装过程中作为内引线位移，内引线剥离等的不整合点，以便加强基底基板2的自由区域2a，使得高粘合精度可以通过抑制在该自由区域2a的部分产生的弹性来实现。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2007027685A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007027685A
公开(公告)日：2007-02-01
申请号：JP2006102611
申请日：2006-04-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： WATASE KAZUMI , NAKAMURA AKIO , OTANI KATSUMI
IPC分类号： H01L21/66 , H01L21/3205 , H01L23/52
CPC分类号： H01L22/14 , G01R31/2853 , H01L23/3114 , H01L23/5228 , H01L2924/0002 , H01L2924/014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for manufacturing the semiconductor device for detecting the failure of metal wiring with good accuracy by performing the electrical test of the metal wiring during a process in a semiconductor wafer status, for quickly and accurately specifying the factor of the failure, and for feeding it back to the process when the failure of the metallic wiring is generated.
SOLUTION: Metal wiring 14 for inspection and an electrode 16 for inspection electrically detect the open failure, short-circuit failure, leakage failure of metal wiring 13, and connection failure between an element electrode 11 and the metal wiring 13; and are formed on the region of a semiconductor substrate 10 where the metal wiring 13 and an electrode 15 for external connection are not formed. The semiconductor wafer is subjected to an electrical test so that it is possible to detect the aforementioned failures with good accuracy during a manufacturing process. Also, the electrical test is executed so that it is possible to quickly and accurately confirm the factors of those failures, and to attain early feedback to a process.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供半导体器件和制造半导体器件的方法，用于通过在半导体晶片状态的处理期间执行金属布线的电气测试，以高精度检测金属布线的故障，为快速准确地指定故障的因素，并且在产生金属布线的故障时将其馈送回该过程。解决方案：用于检查的金属布线14和用于检查的电极16电检测金属布线13的开路故障，短路故障，泄漏故障以及元件电极11与金属布线13之间的连接故障; 形成在不形成金属配线13和外部连接用电极15的半导体基板10的区域。对半导体晶片进行电气测试，使得可以在制造过程中以高精度检测上述故障。此外，执行电气测试，使得可以快速且准确地确认这些故障的因素，并且对过程进行早期反馈。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2005340588A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005340588A
公开(公告)日：2005-12-08
申请号：JP2004158966
申请日：2004-05-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KUWABARA KIMIHITO , OTANI KATSUMI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/16225 , H01L2224/73204 , H01L2924/15311
摘要： PROBLEM TO BE SOLVED: To realize the wiring of a narrow pitch without giving a damage to a solder connecting part to a mother circuit board due to a thermal expansion difference of a mold sealing resin and a substrate.
SOLUTION: A laminated semiconductor device includes a substrate 3 having a wiring layer and the solder connecting part 12 provided on a lower surface, and at least two or more semiconductor elements including a first semiconductor element 8 and a second semiconductor element 6 laminated on the substrate 3. The semiconductor device further includes a wiring film 14 having at least two or more layers of wiring conductors 17-b, 17-c. The first semiconductor element 8 is connected to the wiring conductor 17-c of the wiring film 14. The second semiconductor element 6 is connected to another wiring conductor 17-b at the opposite side of the wiring film surface connected with the first semiconductor element 8. Furthermore, the wiring conductor 17-b, 17-c are connected to the substrate 3.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：由于模具密封树脂和基板的热膨胀差异，实现窄间距的布线而不会损坏到母电路板的焊料连接部分。解决方案：层叠半导体器件包括具有布线层的基板3和设置在下表面上的焊料连接部12，以及包括第一半导体元件8和第二半导体元件6的至少两个以上的半导体元件层叠半导体器件还包括具有至少两层或多层布线导体17-b，17-c的布线膜14。第一半导体元件8连接到布线膜14的布线导体17-c。第二半导体元件6与布线膜表面的与第一半导体元件8连接的相反侧的另一布线导体17-b连接此外，布线导体17-b，17-c连接到基板3.版权所有（C）2006，JPO＆NCIPI

6. 发明专利

JP2008103434A Semiconductor device and temperature evaluation method thereof, and lead frame for temperature evaluation method 审中-公开
标题翻译：半导体器件及其温度评估方法及温度评估方法的引线框架
公开(公告)号：JP2008103434A
公开(公告)日：2008-05-01
申请号：JP2006283175
申请日：2006-10-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI
IPC分类号： H01L23/34 , H01L23/50
CPC分类号： H01L2224/32245
摘要： PROBLEM TO BE SOLVED: To evaluate temperature in a semiconductor chip sealed with resin easily and precisely. SOLUTION: In a semiconductor device, the semiconductor chip 6 is connected to a lead 3 for external connection electrically, and is sealed with a sealing resin 9. A suspension lead 2 extended from a die pad 1 connected to the semiconductor chip 6 thermally is exposed from the surface of the sealing resin 9 partially, and a thermo material 10 changing its color according to the temperature is provided in the exposed section. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：评估用树脂密封的半导体芯片中的温度容易且精确地评估。解决方案：在半导体器件中，半导体芯片6与用于外部连接的引线3电连接，并用密封树脂9密封。从连接到半导体芯片6的管芯焊盘1延伸的悬置引线2 热部分地从密封树脂9的表面露出，并且在暴露部分中提供根据温度改变其颜色的热敏材料10。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2007194379A Lead frame, semiconductor device, and method of manufacturing same 审中-公开
标题翻译：引线框架，半导体器件及其制造方法
公开(公告)号：JP2007194379A
公开(公告)日：2007-08-02
申请号：JP2006010552
申请日：2006-01-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI , SAKOTA HIDEKI
IPC分类号： H01L23/50
CPC分类号： H01L2224/48095 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2924/181 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a lead frame which is capable of preventing the peripheral part of a semiconductor chip from being tilted or deformed, when the semiconductor chip mounted on the set-up center mount of a die pad is connected to signal leads with bonding wires. SOLUTION: The die pad 2 mounted with the semiconductor chip is supported by suspension leads 3, signals leads 4 are arranged around the die pad 2, the center mount 2a of the die pad 2 is set up higher than the peripheral part 2b of the die pad 2 so as to protrude upwards, and wing-shaped members 6 for supporting the semiconductor chip mounted on the center mount 2a are provided around the peripheral sides of the die pad 2. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够防止半导体芯片的周边部分倾斜或变形的引线框架，当安装在管芯焊盘的安装中心安装件上的半导体芯片连接到信号引线与接合线。
解决方案：安装有半导体芯片的管芯焊盘2由悬挂引线3支撑，信号引线4布置在管芯焊盘2周围，管芯焊盘2的中心安装件2a被设置为高于外围部分2b ，并且在芯片垫2的周边设置用于支撑安装在中心安装部2a上的半导体芯片的翼状部件6。（C）2007， JPO＆INPIT

8. 发明专利

JP2007042957A Method for partially plating multilayer substrate for semiconductor device 审中-公开
标题翻译：用于半导体器件的多层基板的局部放电方法
公开(公告)号：JP2007042957A
公开(公告)日：2007-02-15
申请号：JP2005227322
申请日：2005-08-05
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI
IPC分类号： H05K3/22 , H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for partially plating a multilayer substrate for a semiconductor device by which no power supply wires for plating are formed on patterns on the surface of the substrate, the flexibility of substrate wiring design is improved, and the multilayer substrate hardly affecting high-frequency signals can be formed. SOLUTION: The multilayer substrate for the semiconductor device has: linear wires 2 and vias 1 for wiring connected with their ends which are formed on the surface of an insulating substrate 3; and a semiconductor chip with circuit elements formed therein is mounted on the substrate. When the substrate is manufactured, partial plating is performed by connecting the linear wires 2 formed on the surface of the substrate with a land pattern 4 for reference potential which is arranged in the center of the multilayer substrate for the semiconductor device by power supply wires 6 for plating, and feeding the linear wires 2 from an intermediate conductor layer 9 through vias 5 for reference potential and the land pattern 4 for reference potential. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决问题的方案：为了提供一种半导体器件的多层基板的方法，该半导体器件的多层基板在基板的表面上的图案上不形成用于电镀的电源线，所以提高了基板布线设计的灵活性，并且可以形成几乎不影响高频信号的多层基板。解决方案：用于半导体器件的多层基板具有：在绝缘基板3的表面上形成的用于与端部连接的布线的线状布线2和通孔1; 并且其上形成有电路元件的半导体芯片安装在基板上。当制造基板时，通过将形成在基板表面上的线性线2与布置在用于半导体器件的多层基板的中心的参考电位的焊盘图案4连接，通过电源线6进行部分电镀用于电镀，并将线性导线2从中间导体层9通过用于参考电位的通孔5和用于参考电位的焊盘图案4。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2005011906A Lead frame and its manufacturing method, and semiconductor device 审中-公开
标题翻译：引线框架及其制造方法及半导体器件
公开(公告)号：JP2005011906A
公开(公告)日：2005-01-13
申请号：JP2003172467
申请日：2003-06-17
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI
IPC分类号： H01L23/50
CPC分类号： H01L2224/48091 , H01L2224/48247 , H01L2224/48257 , H01L2224/49171 , H01L2224/73265 , H01L2924/181 , H01L2924/00 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To increase a degree of freedom in arranging electrode pads on a semiconductor chip by reducing restrictions by the arrangement of external connection leads. SOLUTION: A lead frame (100) has the external connection leads (1) whose each one end is connected to a frame (4) and the other end is extended near the center, and which have regions for holding semiconductor chips. At least a wire bonding region in an inner lead (2) of the external connection lead is formed in such a shape as to be substantially parallel or vertical to end sides of the semiconductor chip. COPYRIGHT: (C)2005,JPO&NCIPI

10. 发明专利

JP2008252054A Semiconductor device and method for manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2008252054A
公开(公告)日：2008-10-16
申请号：JP2007147571
申请日：2007-06-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI
IPC分类号： H01L23/28 , H01L21/56 , H01L23/12 , H01L23/29
CPC分类号： H01L21/565 , H01L24/73 , H01L2224/32225 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/16251 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device of stable quality that prevents the short-circuiting of metal thin wires caused by the flowage of resin at the time of sealing, improves radiation property, and produces no thin burrs in the semiconductor device, where a part of a thermal conductor is exposed to the outside from a sealant resin and a method for manufacturing the same. SOLUTION: The semiconductor device including the semiconductor 1, a thermal conductor 91 disposed facing a principal plane of the semiconductor 1, and the sealant resin that seals at least a part of the semiconductor device 1 and a part of the thermal conductor 91, with a plane facing the principal plane of the semiconductor device 1, in the thermal conductor 91 and a part of the plane on the opposite side exposed to the outside from the sealant resin 6, wherein an opening 11 that penetrates in the plate width direction is provided on a part of the plane, on which an exposed section of the thermal conductor 91 is provided; and a protrusion section 91b that protrudes to a side opposite to the side on which the semiconductor device 1 is disposed is provided at a circumference of the opening 11. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种质量稳定的半导体器件，其防止在密封时树脂流动导致的金属细线短路，提高辐射性能，并且在半导体中不产生薄的毛刺装置，其中热导体的一部分从密封树脂暴露于外部及其制造方法。解决方案：包括半导体1的半导体器件，面向半导体1的主平面设置的热导体91和密封半导体器件1的至少一部分的密封树脂和热导体91的一部分面向半导体器件1的主平面的平面，热导体91中的与密封树脂6暴露于外侧的相对侧的平面的一部分，其中穿过板宽度方向的开口11 设置在所述平面的一部分上，在其上设置有热导体91的暴露部分; 并且在开口11的圆周处设置有突出到与设置有半导体器件1的一侧相对的一侧的突出部91b。版权所有（C）2009，JPO＆INPIT

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