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1. 发明专利

JP2008059638A Music reproducing device and music reproducing terminal 有权
标题翻译：音乐再现设备和音乐再现终端
公开(公告)号：JP2008059638A
公开(公告)日：2008-03-13
申请号：JP2006232366
申请日：2006-08-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HIRATA TOMOHIRO , FUJIWARA MUTSUMI , UDA KENICHIRO
IPC分类号： G11B20/10 , G10K15/04
CPC分类号： G11B27/105 , G11B2220/61 , H04M1/72558 , H04N5/907 , Y02D70/00
摘要： PROBLEM TO BE SOLVED: To solve the problem that music can not be reproduced for a long period of time when an audio file is reproduced since a single high-performance LSI performs all necessary processings including header analysis and audio data reproduction processing, thereby increasing a processing load and power consumption. SOLUTION: A storage device 30 has a storage region of an audio file and a header analysis result storage part 31. A first LSI 10 reads a header Ah of the audio file from the storage device 30 and analyzes it, after storing a header analysis result in the storage device 30 of the header analysis storage part 31, the LSI 10 is shifted to a power saving state. A second LSI 20 reads audio data AD held in the storage device 30 and processes it based on the header analysis result stored in the header analysis result storage part 31 of the storage device 30 in the power saving state of the first LSI10. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决由于单个高性能LSI执行包括标题分析和音频数据再现处理的所有必要处理而在再现音频文件的长时间内不能再现音乐的问题，从而增加处理负荷和功耗。解决方案：存储装置30具有音频文件的存储区域和头部分析结果存储部分31.第一LSI 10从存储装置30读取音频文件的头部Ah，并在存储装置30之后对其进行分析标题分析结果导致标题分析存储部分31的存储装置30中，LSI 10转移到省电状态。第二LSI20读取保存在存储装置30中的音频数据AD，并且在第一LSI10的省电状态下，基于存储在存储装置30的标题分析结果存储部31中的标题分析结果进行处理。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006285835A Method for evaluating power consumption and system for evaluating power consumption 审中-公开
标题翻译：用于评估消耗功率的方法和用于评估功耗的系统
公开(公告)号：JP2006285835A
公开(公告)日：2006-10-19
申请号：JP2005107371
申请日：2005-04-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UDA KENICHIRO
IPC分类号： G06F17/50 , G01R31/28 , H01L21/82
摘要： PROBLEM TO BE SOLVED: To accelerate the evaluation of power consumption while using a logic emulator corresponding to an actual circuit scale without adding a circuit for measuring power consumption in a largely scaled integrated circuit.
SOLUTION: A method for evaluating power consumption is provided which divides a largely scaled integrated circuit, and creates a power consumption value table PT for each of the divided blocks in advance. A logic emulation device 30 records only the toggle information TI of a necessary node, and calculates overall power consumption evaluation by using the toggle information TI and the power consumption value table PT. Thus, it is possible to accelerate the power consumption evaluation by using a logic emulation device without adding an excess logic circuit.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了在使用与实际电路规模相对应的逻辑仿真器的情况下加快对功耗的评估，而不添加用于测量大规模集成电路中的功耗的电路。提供一种用于评估功耗的方法，其分割大部分缩放的集成电路，并且预先为每个划分的块创建功耗值表PT。逻辑仿真装置30仅记录所需节点的切换信息TI，并且通过使用切换信息TI和功耗值表PT来计算总体功耗评估。因此，可以通过使用逻辑仿真装置来加速功耗评估，而不增加多余的逻辑电路。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2008054090A Controller 审中-公开
标题翻译： CONTROLLER
公开(公告)号：JP2008054090A
公开(公告)日：2008-03-06
申请号：JP2006228951
申请日：2006-08-25
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SATO TAKESHI , UDA KENICHIRO , FUJIWARA MUTSUMI
IPC分类号： H04L9/10 , G06K17/00
CPC分类号： H04L9/0894 , H04L9/3273 , H04L2209/603
摘要： PROBLEM TO BE SOLVED: To provide a controller that makes a reduction in number of times of mutual authentication in-between a recording medium compatible with low power consumption. SOLUTION: The controller executes data-reading from the recording medium with which authentication is mutually executed, or data-writing to the recording medium. The controller is provided with an interface part being an interface in-between the recording medium, a storage part for storing key data and authentication information that are generated when authentication is executed, and a control part that controls power supply corresponding to whether or not the controller executes the data-reading from the recording medium or the data-writing to the recording medium. While the controller does not execute the data-reading from the recording medium or the data-writing to the recording medium, the control part controls so as to supply the power supply only to the storage part. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种在兼容低功耗的记录介质之间减少相互认证次数的控制器。解决方案：控制器从相互执行认证的记录介质执行数据读取，或者对记录介质进行数据写入。控制器设置有接口部分，该接口部分是记录介质之间的接口，用于存储密钥数据的存储部分和在认证执行时产生的认证信息;以及控制部分，其控制与是否控制器从记录介质执行数据读取或对记录介质的数据写入。当控制器不执行从记录介质的数据读取或对记录介质的数据写入时，控制部分控制以仅向存储部分提供电源。版权所有（C）2008，JPO＆INPIT

4. 发明专利

JP2008060653A Control device 审中-公开
标题翻译：控制装置
公开(公告)号：JP2008060653A
公开(公告)日：2008-03-13
申请号：JP2006231854
申请日：2006-08-29
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： SATO TAKESHI , UDA KENICHIRO , FUJIWARA MUTSUMI
IPC分类号： H04L9/10
CPC分类号： G11B20/00086 , G11B20/0021 , G11B20/00253 , G11B20/00442 , G11B20/10527 , G11B2020/1062 , G11B2020/10685 , G11B2020/10759 , H04L9/0637 , H04L9/0894 , H04L9/32 , H04L2209/60
摘要： PROBLEM TO BE SOLVED: To provide a control device which encrypts or decrypts a plurality of contents in parallel.
SOLUTION: The control device reads out data from a recording medium or writes data into the recording medium. The control device is provided with a plurality of processing parts for performing at least one of encryption and decryption; a plurality of interface parts that is interface to the recording medium; and a control part for assigning one of the plurality of processing parts and one of the plurality of interface parts for each classification of contents read out from the recording medium or of contents to be written to the recording medium.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供并行地对多个内容进行加密或解密的控制装置。解决方案：控制装置从记录介质读出数据或将数据写入记录介质。所述控制装置设置有用于执行加密和解密中的至少一个的多个处理部分; 与记录介质接口的多个界面部分; 以及控制部分，用于从用于从记录介质读出的每个内容分类或要写入到记录介质的内容中分配多个处理部分中的一个和多个接口部分中的一个。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2008052817A Recording and reproducing device and companion system 审中-公开
标题翻译：记录和复制设备和公司系统
公开(公告)号：JP2008052817A
公开(公告)日：2008-03-06
申请号：JP2006227698
申请日：2006-08-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OKAYA YOSHIHISA , SATO TAKESHI , NAKAHARA MITSUNARI , UDA KENICHIRO
IPC分类号： G11B20/10 , H04N5/85 , H04N5/937
CPC分类号： G11B20/10527 , G11B2020/10685 , G11B2020/10694 , G11B2020/10731 , G11B2020/10962
摘要： PROBLEM TO BE SOLVED: To attain reading or writing of an arbitrary data from/to a same recording medium when reproducing a stream data recorded in the recording medium or recording a stream data to the recording medium, moreover, to attain suppression of a buffer capacity for recording or reproduction.
SOLUTION: A recording and reproducing apparatus is characterized by comprising: a recording medium control part 4 for reading/writing a data from/to a memory card 20; a buffer 5a for reproduction and a buffer 6b for reading which store a stream data among the data read/written by the recording medium control part; a reproduction processing part 6a which decodes the stream data stored in the buffer to perform reproduction; a recording processing part 6b which encodes a video and a voice signal; and an access management part 2 which controls timing of switching access to the buffer and memory without breaking recording or reproduction processing while monitoring the buffer state during recording and reproduction of the stream data, and manages the memory and the recording medium control part in transaction units.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了在再现记录在记录介质中的流数据或者将流数据记录到记录介质上时，从同一记录介质读取或写入任意数据，此外，为了达到抑制用于记录或再现的缓冲器容量。解决方案：记录和再现装置的特征在于包括：用于从存储卡20读取/写入数据的记录介质控制部分4; 用于再现的缓冲器5a和用于读取的缓冲器6b，其存储由记录介质控制部分读/写的数据中的流数据; 对存储在缓冲器中的流数据进行解码以进行再现的再现处理部分6a; 编码视频和语音信号的记录处理部分6b; 以及访问管理部分2，其在监视流数据的记录和再现期间的缓冲状态的同时，控制切换对缓冲器和存储器的访问的定时，而不中断记录或再现处理，并且以交易单元管理存储器和记录介质控制部分。版权所有（C）2008，JPO＆INPIT

6. 发明专利

JP2007103662A Semiconductor integrated circuit and its manufacturing method 审中-公开
标题翻译：半导体集成电路及其制造方法
公开(公告)号：JP2007103662A
公开(公告)日：2007-04-19
申请号：JP2005291340
申请日：2005-10-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHIMURA TAKASHI , UDA KENICHIRO , HIRANO YOKO , FUJIMURA KATSUYA , HAMAGUCHI KAZUMI , AZUMA KENICHIRO
IPC分类号： H01L21/82 , G01R31/28 , H01L21/822 , H01L27/04
CPC分类号： G01R31/2884 , G01R31/318364
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device equipped with a test circuit of high performance while suppressing the increase of an occupied area. SOLUTION: The arranging positions of a cell constituting a test objective circuit, and a non-connected cell prepared for the constitution of the test circuit, are determined and, thereafter, the connecting relation of the non-connected cell prepared for the constitution of the test circuit is determined based on these arrangement informations to constitute the test circuit, whereby the semiconductor integrated circuit is provided as equipped with the test circuit. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种配备有高性能测试电路的半导体集成电路器件，同时抑制占用面积的增加。＆lt; P＆gt;解决方案：确定构成测试对象电路的单元的布置位置和为测试电路构成而准备的非连接单元，然后确定准备用于测试对象电路的非连接单元的连接关系基于构成测试电路的这些配置信息来确定测试电路的结构，由此提供配备有测试电路的半导体集成电路。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2008052487A Digital signal processing apparatus and digital signal processing terminal 审中-公开
标题翻译：数字信号处理设备和数字信号处理终端
公开(公告)号：JP2008052487A
公开(公告)日：2008-03-06
申请号：JP2006227699
申请日：2006-08-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HAYASHIBARA KEIJI , UDA KENICHIRO , FUJIWARA MUTSUMI
IPC分类号： G06F1/04 , H03M7/30 , H04L9/10
摘要： PROBLEM TO BE SOLVED: To reduce an effective system clock frequency without using a PLL circuit to reduce power consumption and storage capacity. SOLUTION: A digital signal processing apparatus includes: a storage device control part 31 for reading encrypted data from a storage device 2; a first storage part 32 for buffering the encrypted data read by the storage device control part 31 from the storage device; a decrypting process part 33 for reading the encrypted data from the first storage part 32 and decrypting the data; a second storage part 34 for buffering the data decrypted by the decrypting process part 33; a decoding process part 35 for reading the decrypted data from the second storage part 34 and decoding the data; and a data transfer control part 36 for accepting a data transfer request from the decoding process part 35 and instructing the decrypting process part 33 to transfer the data to the decoding process part, and for accepting a data transfer request from the decrypting process part 33 and instructing the storage device control part 31 to transfer the data to the decrypting process part. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了降低有效的系统时钟频率，而不使用PLL电路来降低功耗和存储容量。解决方案：数字信号处理装置包括：存储装置控制部分31，用于从存储装置2读取加密数据; 第一存储部分32，用于将由存储装置控制部分31读取的加密数据从存储装置中缓存; 解密处理部33，用于从第一存储部32读取加密数据，对数据进行解密; 用于缓存由解密处理部分33解密的数据的第二存储部分34; 解码处理部35，用于从第二存储部34读取解密数据，对数据进行解码; 以及数据传送控制部分36，用于接受来自解码处理部分35的数据传送请求，并指示解密处理部分33将数据传送到解码处理部分，并且从解密处理部分33接受数据传送请求;以及指示存储装置控制部31将数据传送到解密处理部。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2004111609A Power supply path structure in integrated circuit design 有权
公开(公告)号：JP2004111609A
公开(公告)日：2004-04-08
申请号：JP2002271362
申请日：2002-09-18
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： UDA KENICHIRO
IPC分类号： H01L21/822 , G11C11/4074 , H01L21/82 , H01L23/528 , H01L27/04
CPC分类号： G11C11/4074 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To enable the estimation of the charging/discharging time and power consumption of the power supply voltage control object portion in the design of an integrated circuit in the stage before the completion of cell arrangement.
SOLUTION: For the power supply path 10 in the side of the high potential side power supply VDD and the power supply path 20 in the side of the low potential side power supply VSS, the interval of those adjacent to a plurality of lead-out portions 11, 12, 13 and 21, 22, 23 branched from the main lines 10a, 20a of the power supply paths 10, 20 are set equally. The branching positions of the lead-out portions 11, 12, 13 are matched with the branching positions of the lead-out portions 21, 22, 32 in the longitudinal direction of the power supply paths. The lead-out length of the lead-out portions 11, 12, 13 is set longer than than the lead-out length of the lead-out portions 21, 22, 23, widths of the lead-out portions 11, 12, 13 and 21, 22, 23 are set equal with each other and is also set smaller than an interval between the adjacent lead-out portions.
COPYRIGHT: (C)2004,JPO

9. 发明专利

JP2001278712A ANTIBACTERIAL AND ANTIFUNGAL AGENT, ANTIBACTERIAL AND ANTIFUNGAL AGENT FOR FILTER AND DEPURATIVE FILTER 失效
公开(公告)号：JP2001278712A
公开(公告)日：2001-10-10
申请号：JP2000095459
申请日：2000-03-30
申请人： YUSHIRO CHEM IND , MATSUSHITA ELECTRIC IND CO LTD
发明人： KIMURA MASAHIRO , YOSHIDA RYOHEI , MUTO TOSHIMI , ONO HAJIME , UDA KENICHIRO
IPC分类号： B01D39/14 , A01N59/06
摘要： PROBLEM TO BE SOLVED: To provide an antibacterial and antifungal agent and an antibacterial and antifungal agent for filters which have an excellent preventive action on the propagation of not only bacteria but also mold and/or mildew and does not cause global environment damage, and to provide a depurative filter using the same agents. SOLUTION: This antibacterial and antifungal agent and that for filters contain at least one of calcium compounds. Calcium oxide exhibits effect especially on Escherichia coli, Staphylococcus aureus and mold fungi, and such natural calcium compounds as are exemplified by Spisula sachalinensis are suitable. Such powder particles as have a particle diameter of 0.01-100 μm exhibit especially excellent characteristics. This depurative filter formed by sticking the above agent on a filter material can be used.

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