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1. 发明专利

JP2005208702A Portable information terminal 审中-公开
标题翻译：便携式信息终端
公开(公告)号：JP2005208702A
公开(公告)日：2005-08-04
申请号：JP2004011360
申请日：2004-01-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： IMOTO TOMOYUKI
IPC分类号： G06F1/26 , G06F1/16 , H04M1/02 , H04M1/21 , H04M1/73
摘要： PROBLEM TO BE SOLVED: To solve the problems wherein, when conventional cellular phone terminals are used to pick up a moving image, the imaging time is relatively short, and the absence of an optical zoom mechanism disables a high image quality zoom. SOLUTION: A portable information terminal comprises: a portable information terminal body comprising at least first storing means, a first input operation part, a first display part, a first power source part and a first camera part; and an extension unit comprising at least a second power source part and a second camera part having an optical zoom function. The extension unit is removably attachable to the portable information terminal body, and while the extension unit is attached to the portable information terminal body, the extension unit can supply power from the second power source part and send image data from the second camera part, both to the portable information terminal body. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了解决当传统的蜂窝电话终端用于拾取运动图像时，成像时间相对较短，并且没有光学变焦机构禁止高图像质量变焦的问题。解决方案：便携式信息终端包括：便携式信息终端主体，包括至少第一存储装置，第一输入操作部分，第一显示部分，第一电源部分和第一相机部分; 以及包括至少第二电源部分和具有光学变焦功能的第二相机部件的扩展单元。扩展单元可移动地附接到便携式信息终端主体，并且当扩展单元附接到便携式信息终端主体时，扩展单元可以从第二电源部分提供电力并从第二相机部分发送图像数据到便携式信息终端机身。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2006331107A Electric power management circuit and electronic circuit 审中-公开
标题翻译：电力管理电路和电子电路
公开(公告)号：JP2006331107A
公开(公告)日：2006-12-07
申请号：JP2005154227
申请日：2005-05-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： IMOTO TOMOYUKI , MIYAJIMA HIROSHI
IPC分类号： G06F1/32 , G06F1/04
摘要： PROBLEM TO BE SOLVED: To provide an electric power management circuit which improves a processing speed of electronic equipment while restraining total electric power consumption of a plurality of function blocks inside the electronic equipment under permissible electric power, and also provide an electronic circuit. SOLUTION: The electric power management circuit 2 manages the electric power of a plurality of function blocks 6, 7 and 8. Each of the function blocks 6, 7 and 8 operates in a plurality of operating states which change by a state transition. The operating states of the blocks 7, 8 and 9 transit when they output state transition request signals 9, which requests state transitions, to the electric power management circuit 2 and acquire the permission for the state transitions from the electric power management circuit 2. The electric power management circuit 2 is provided with a computing part 3 which computes a posterior-to-transition power consumption value 13, which is a total power consumption value of the plurality of function blocks after their states transit, based on the state transition request signals 9; and a permission part 4 which permits the state transitions based on the state transition request signals 9 when the posterior-to-transition power consumption value 13 is at most a prescribed permissible electric power value 5. By this, an operational speed can be improved without exceeding permissible electric power of electronic equipment. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种电力管理电路，其在允许电力下限制电子设备内的多个功能块的总电力消耗的同时提高电子设备的处理速度，并且还提供电子电路。解决方案：电力管理电路2管理多个功能块6,7和8的电力。功能块6,7和8中的每一个以多个操作状态操作，这些状态由状态转换。当它们向电力管理电路2输出请求状态转换的状态转移请求信号9并且从电力管理电路2获取状态转换的许可时，块7,8和9的操作状态转移。电力管理电路2设置有计算部件3，该计算部件3基于状态转换请求信号计算作为其状态转移后的多个功能块的总功耗值的后转换功耗值13 9; 以及允许部分4，当后转换功耗值13最多达到规定的允许电力值5时，允许基于状态转换请求信号9的状态转换。由此，可以在没有超过电子设备的允许电力。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2005092779A Image processing system, and method for transferring image data 审中-公开
标题翻译：图像处理系统和用于传输图像数据的方法
公开(公告)号：JP2005092779A
公开(公告)日：2005-04-07
申请号：JP2003328767
申请日：2003-09-19
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHIDA KENICHI , IMOTO TOMOYUKI , INOUE AKIHIKO , KIMURA TOMOO , HASHIMOTO TAKASHI , SUGISAWA YASUSHI , FUJIMOTO HITOSHI
IPC分类号： G06T1/20
摘要： PROBLEM TO BE SOLVED: To provide an image processing system and an image data transfer method for reducing costs by using an image processing LSI where the number of inputting and outputting terminals is reduced.
SOLUTION: The image processing system is provided with an LSI 100, a data bus 110, m pieces of imaging devices 120 to 130, and n pieces of display devices 140 to 150. The LSI 100 is connected with the data bus 110 through an I/O interface 102 and an I/O terminal 101. Both of the m pieces of imaging devices 120 to 130 and the n pieces of display devices 140 to 150 are connected to the common data bus 110. The data of an image picked up with the first imaging device 120 is sent to the data bus 110, and taken into the LSI 100 via the I/O terminal 101 and the I/O interface 102 to apply image processing to the data. The processed image data are sent to the data bus 110 via the I/O interface 102 and the I/O terminal 101, taken into the first display device 140 and displayed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种通过使用减少输入和输出端子数量的图像处理LSI来降低成本的图像处理系统和图像数据传送方法。解决方案：图像处理系统设置有LSI 100，数据总线110，m个成像设备120至130以及n个显示设备140至150. LSI 100与数据总线110连接通过I / O接口102和I / O端子101. m个成像装置120至130和n个显示装置140至150中的每一个连接到公共数据总线110.图像的数据拾取与第一成像装置120一起发送到数据总线110，并且经由I / O终端101和I / O接口102进入LSI 100以对数据应用图像处理。经处理的图像数据经由I / O接口102和I / O终端101发送到数据总线110，并被输入到第一显示装置140中并被显示。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2008039724A Semiconductor device and device of observing internal state of semiconductor 审中-公开
标题翻译：半导体器件和半导体内部状态的器件
公开(公告)号：JP2008039724A
公开(公告)日：2008-02-21
申请号：JP2006218043
申请日：2006-08-10
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHII MASAHIRO , NAKAYAMA TAKESHI , IMOTO TOMOYUKI
IPC分类号： G01R31/319 , G01R31/28 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To solve the problem that it is difficult to know correlation between malfunction and instability in a power source due to insufficiency of means for observing the instability in the power source inside a system LSI although one of causes of malfunction of the LSI is instability of internal power supply voltage and the tendency gets further worse due to speedup and reduction in voltage in recent years.
SOLUTION: A circuit for generating a trigger signal when a fluctuation of the power source at each functional block power supply terminal position inside the system LSI exceeds a certain amount is constituted by resistive voltage division and incorporation of a comparator. By inputting the trigger signal into an internal signal observation control circuit of the system LSI, respective internal states during the fluctuation of the power source are output to the outside of SOC.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了解决由于用于观察系统LSI内部的电源的不稳定性的装置不足而难以知道电源的故障和不稳定性之间的相关性的问题，尽管存在故障原因之一的LSI内部电源电压不稳定，近年来由于加速和降低电压而导致的趋势进一步恶化。解决方案：当系统LSI内的每个功能块电源端子位置处的电源的波动超过一定量时，产生触发信号的电路由电阻分压和比较器的结合构成。通过将触发信号输入到系统LSI的内部信号观测控制电路中，电源波动期间的各自的内部状态被输出到SOC的外部。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2004246402A Method and device for optimizing logical circuit, and device for synthesizing same 有权
标题翻译：用于优化逻辑电路的方法和装置，以及用于合成其逻辑电路的装置
公开(公告)号：JP2004246402A
公开(公告)日：2004-09-02
申请号：JP2003032438
申请日：2003-02-10
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KIMURA TOMOO , ISHIDA KENICHI , IMOTO TOMOYUKI
IPC分类号： G06F9/455 , G06F17/50 , H03K19/00 , H03K19/173
CPC分类号： G06F17/505
摘要： PROBLEM TO BE SOLVED: To provide a logical circuit optimizing method for improving efficiency in using variable logical elements of a logical emulation device.
SOLUTION: A division flip-flop FF2 is inserted to a cluster C having a cluster length which is larger than the predetermined cluster length. The cluster C with the flip-flop inserted therein is re-clustered, so as to acquire segmentalized clusters C1, C2. Thus, flexibility is improved when the clusters are allocated to the variable logical elements (e.g., FPGA) of the logical emulation device.
COPYRIGHT: (C)2004,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于提高使用逻辑仿真装置的可变逻辑元件的效率的逻辑电路优化方法。解决方案：分割触发器FF2被插入到具有大于预定簇长度的簇长度的簇C中。将其中插入有触发器的簇C重新聚集，以便获得分段化的簇C1，C2。因此，当将集群分配给逻辑仿真设备的可变逻辑元件（例如FPGA）时，灵活性得到改善。版权所有（C）2004，JPO＆NCIPI

6. 发明专利

JP2003337845A Emulation device and emulation method 审中-公开
标题翻译：仿真器件和仿真方法
公开(公告)号：JP2003337845A
公开(公告)日：2003-11-28
申请号：JP2002146341
申请日：2002-05-21
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ISHIDA KENICHI , IMOTO TOMOYUKI , KIMURA TOMOO
IPC分类号： G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide an emulation device capable of shortening a verification time by efficiently verifying a logical circuit.
SOLUTION: A retrieval engine part 9 retrieves the waveform data of an internal signal being a key in analyzing the failure of a logical circuit to be verified from a result waveform data base part 6 to detect a failure occurrence point. A waveform display control part 7 makes a display device 8 display waveform data positioned at the failure occurrence point from the result waveform data base part 6. Therefore, it is possible to obtain waveform data being the key in analyzing the failure of the logical circuit without re-executing emulation. Also, it is possible to save any labor to search the waveform data being the key in analyzing the failure of the logical circuit from the huge waveform data stored in the result waveform data base part 6.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供能够通过有效地验证逻辑电路来缩短验证时间的仿真装置。解决方案：检索引擎部分9检索作为键的内部信号的波形数据，以从结果波形数据库部分6分析要验证的逻辑电路的故障，以检测故障发生点。波形显示控制部7使显示装置8从结果波形数据基部6显示位于故障发生点的波形数据。因此，可以获得作为分析逻辑电路的故障的关键的波形数据，而没有重新执行仿真。此外，可以节省任何劳动力来搜索作为分析逻辑电路的故障的关键的波形数据从存储在结果波形数据库部分6中的巨大波形数据。版权所有（C）2004， JPO

7. 发明专利

JP2003273726A Logic emulation device 有权
标题翻译：逻辑仿真器件
公开(公告)号：JP2003273726A
公开(公告)日：2003-09-26
申请号：JP2002068714
申请日：2002-03-13
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： IMOTO TOMOYUKI , ISHIDA KENICHI , KIMURA TOMOO
IPC分类号： G06F9/455 , G06F17/50 , H01L21/82 , H03K19/173
CPC分类号： G06F17/5022
摘要： PROBLEM TO BE SOLVED: To provide a logic emulation device capable of efficiently utilizing signal lines. SOLUTION: Respective terminals 44-1 to 44-n of a terminal group 44 of a variable wiring element 40 are connected to three corresponding signal lines 12-1 to 12-n, 22-1 to 22-n, 32-1 to 32-n among three variable logic elements 10, 20, 30. The signal lines 12-1 to 12-n, 22-1 to 22-n, 32-1 to 32-n connected to respective terminals 44-1 to 44-n of the terminal group 44 of the variable wiring element 40 can be used for any variable logic elements 10, 20, 30. Since signal lines can be selected and utilized in accordance with the number of signal lines used for respective variable logic elements 10, 20, 30 determined on the basis of a result of dividing a circuit to be verified, the signal lines can be efficiently utilized. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供能够有效利用信号线的逻辑仿真装置。
解决方案：可变布线元件40的端子组44的各个端子44-1至44-n连接到三个对应的信号线12-1至12-n，22-1至22-n，32- 3个可变逻辑元件10,20,30中的1〜32-n。信号线12-1〜12-n，22-1〜22-n，32-1〜32-n分别与各个端子44-1〜可变配线元件40的端子组44的44-n可以用于任何可变逻辑元件10,20,30。由于可以根据用于各个可变逻辑元件的信号线的数量来选择和使用信号线基于将被验证的电路分割的结果确定的10,20,30可以有效地利用信号线。版权所有（C）2003，JPO

8. 发明专利

JP2003258618A LOGIC EMULATOR 审中-公开
公开(公告)号：JP2003258618A
公开(公告)日：2003-09-12
申请号：JP2002060839
申请日：2002-03-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： IMOTO TOMOYUKI , ISHIDA KENICHI , KIMURA TOMOO
IPC分类号： H03K19/00 , H03K19/003
摘要： PROBLEM TO BE SOLVED: To provide a logic emulator which avoids flow of an excessively large current, to prevent external devices and the logical emulation device from being damaged, thereby smoothly verifying the circuits under test. SOLUTION: An output control circuit 27 acquires detected temperature data of variable logic elements 20, 21 by temperature detector units 10, 11, and sets the logic elements 20, 21 to high output impedance states, when excessively large currents flow in the logic elements 20, 21 to excessively raise their temperatures. This avoids collisions of signals between the logic elements 20, 21 and collision of signals between each logic circuit 20, 21 and an external device 1, thereby preventing excessively large currents from continuously flowing in the logic elements 20, 21 and the external device 1. COPYRIGHT: (C)2003,JPO

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