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1. 发明专利

JP2005025912A Method and circuit for error correction, error correction encoding, data reproduction or data recording 有权
标题翻译：用于错误校正，错误校正，数据复制或数据记录的方法和电路
公开(公告)号：JP2005025912A
公开(公告)日：2005-01-27
申请号：JP2003374647
申请日：2003-11-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： HASHIMOTO YUICHI , TAKAGI YUJI , USUI MAKOTO , KIMURA NAOHIRO , YAMAMOTO GIICHI
IPC分类号： G11B20/10 , G11B20/12 , G11B20/18
摘要： PROBLEM TO BE SOLVED: To provide a method and a circuit for error correction capable of preventing deterioration of bus accessing, and a method and a circuit for error correction encoding. SOLUTION: Data are read from a recording medium and the reproduced data are deinterleaved and stored in a first memory arbitrating the input/output to/from the first memory is. It is judged whether a predetermined number of data units is stored into the first memory. On the basis of the result data, transfer of the data stored in the first memory to a second memory is permitted. If data transfer is permitted, the reproduced data are transferred from the first memory 11 to the second memory, and input/output to/from the second memory 15 is arbitrated at the transfer. The reproduced data 15 stored in the second memory is then error corrected, and user data contained in the error corrected reproduction data are externally outputted from the second memory 15. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于防止总线访问恶化的纠错方法和电路，以及用于纠错编码的方法和电路。解决方案：从记录介质读取数据，再现数据被解交织并存储在第一存储器中，对第一存储器的输入/输出进行仲裁。判断是否将预定数量的数据单元存储到第一存储器中。基于结果数据，允许将存储在第一存储器中的数据传送到第二存储器。如果允许数据传送，则再现数据从第一存储器11传送到第二存储器，并且在传送时对来自第二存储器15的输入/输出进行仲裁。然后，存储在第二存储器中的再现数据15被纠错，并且包含在纠错再现数据中的用户数据从第二存储器15被外部输出。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2004178789A Reproducing method of recording medium, reproducing control circuit, and reproducing device 审中-公开
公开(公告)号：JP2004178789A
公开(公告)日：2004-06-24
申请号：JP2003379833
申请日：2003-11-10
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： GUSHIMA TOYOJI , USUI MAKOTO , TAKAGI YUJI , HASHIMOTO YUICHI
IPC分类号： H04N5/93 , G11B7/005 , G11B20/10 , G11B20/12 , G11B20/14
摘要： PROBLEM TO BE SOLVED: To secure stable reproducing performance and to reduce omission of data caused by out of synchronism even when the quality of a reproduced signal is deteriorated by the defect of a recording medium or the like. SOLUTION: This method is a reproducing method of a recording medium in which data is recorded with a block unit having a plurality of frames of the prescribed length and position information of the block is recorded. The method comprises a step in which the data and the position information of the block are obtained from the recording medium, a step in which a recording position for each frame in the block is predicted from the position information of the obtained block, a step in which synchronism is obtained with the frame unit from the obtained data, a step in which a storing place for a memory of the data obtained based on the predicted recording position is decided, and a step in which the obtained data is stored in the storing place of the decided memory. COPYRIGHT: (C)2004,JPO

3. 发明专利

JP2005209310A Deinterleave method and circuit, and information reproducing device 审中-公开
标题翻译：消除方法和电路，以及信息再现设备
公开(公告)号：JP2005209310A
公开(公告)日：2005-08-04
申请号：JP2004016787
申请日：2004-01-26
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： TAKAGI YUJI , GUSHIMA TOYOJI , HASHIMOTO YUICHI
IPC分类号： G06F11/08 , G11B20/10 , G11B20/14 , G11B20/18 , H03M13/27
摘要： PROBLEM TO BE SOLVED: To provide an error correction method and circuit which can develop the lost pointers quickly and in a small circuit scale, and also provide an information reproducing device.
SOLUTION: It has a 1st storing step of storing the reproduce data in the storing bank of a 1st memory in the predetermined order, a 1st read step of reading the data in a order different from the storing order, and a 2nd storing step storing the read data in a 2nd memory. If the frames are detected to be out of steps when reproducing the data, the storing position is corrected in inside the storing bank for the following reproduced data.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可以快速和小规模地开发丢失指针的错误校正方法和电路，并且还提供信息再现装置。解决方案：具有第一存储步骤，以预定顺序将再现数据存储在第一存储器的存储库中，第一读取步骤，以与存储顺序不同的顺序读取数据，第二存储步骤将读取的数据存储在第二存储器中。如果在再现数据时检测到帧不符合步骤，则存储位置在存储库的内部被校正以用于以下再现的数据。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2001136078A SYNDROME ARITHMETIC METHOD AND DEVICE 失效
公开(公告)号：JP2001136078A
公开(公告)日：2001-05-18
申请号：JP31534799
申请日：1999-11-05
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SAKAMOTO HIROSHI , MANABE NORIYUKI , HASHIMOTO YUICHI
IPC分类号： G06F11/10 , H03M13/01 , H03M13/15
摘要： PROBLEM TO BE SOLVED: To attain a high-speed syndrome arithmetic operation by extending data whose error is corrected at the same time so as to decrease number of times of accesses to storage means without making syndrome computing elements and their control complicated. SOLUTION: Changeover means 3, 6 that are operated in matching with an error correction data format and number of syndrome computing elements and FIFO storage means 4, 5 with a number of stages similarly in matching therewith are provided to a pre-stage of the syndrome computing elements 7, 8, 9, 10. Thus, the degrees of syndrome coefficients given to each syndrome computing element can be arranged.

5. 发明专利

JPH09297730A METHOD FOR TRANSFERRING DATA THROUGH BUS AND BUS MASTER CONTROLLER 失效
公开(公告)号：JPH09297730A
公开(公告)日：1997-11-18
申请号：JP4830797
申请日：1997-03-03
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HASHIMOTO YUICHI , KAKIAGE TORU , SUZUKI MASATO , KASUGA YOSHIAKI , YASUI JUNICHI
IPC分类号： G06F13/362 , G06F13/28
摘要： PROBLEM TO BE SOLVED: To improve the efficiency of data transfer by releasing a bus corresponding to the presence/absence of request from a 2nd device after the completion of data transfer of a 1st device. SOLUTION: Based on an output 108 of a counter 4, an output 109 of a counter 5 and an output 111 of an intermittent transfer time register 3, a DMA transfer control part 8 discriminates whether the prescribed number of data have been completely transferred in intermittent transfer or not. When it is discriminated that the prescribed number of data have been completely transferred in the intermittent transfer, the DMA transfer control part 8 finishes the assert of a DMA transfer request signal 104 outputted to a bus controller and instructs the release of the bus. When it is discriminated that all the data transfers are completed the DMA transfer control part 8 finishes the assert of the DMA transfer request signal 104 outputted to the bus controller 109 and instructs the release of the bus.

6. 发明专利

JP2002351816A DATA TRANSFER METHOD TROUGH BUS AND BUS MASTER CONTROL DEVICE 审中-公开
公开(公告)号：JP2002351816A
公开(公告)日：2002-12-06
申请号：JP2002145497
申请日：2002-05-20
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HASHIMOTO YUICHI , KAKIAGE TORU , SUZUKI MASATO , KASUGA YOSHIAKI , YASUI JUNICHI
IPC分类号： G06F13/28 , G06F13/362
摘要： PROBLEM TO BE SOLVED: To provide a data transfer method and a bus master control unit having a common bus and enabling to improve data transfer efficiency in both devices. SOLUTION: This is a data transfer method via a bus, and constituted of a stage in which a first device occupies the above bus as a bus master, a stage in which a prescribed number of data are transferred out of the data to be transferred under the state that the above first device occupies the above data, a stage in which the above first device determines whether the above bus to be released or not in accordance with presence of a request from a second device after the end of transfer of prescribed number of above data, and a stage in which the above first device releases the above bus if the above first bus is determined to release the above buss.

7. 发明专利

JPH0773018A REPEAT ARITHMETICAL OPERATION DEVICE 失效
公开(公告)号：JPH0773018A
公开(公告)日：1995-03-17
申请号：JP13527194
申请日：1994-06-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MIYOSHI AKIRA , HASHIMOTO YUICHI
IPC分类号： G06F7/49 , G06F7/487 , G06F7/52
摘要： PURPOSE:To quickly execute the repeat multiplication of normalized floating- point numbers with a small amount of hardware. CONSTITUTION:A mantissa XMk satisfying 1

8. 发明专利

JP2001144627A ERROR CORRECTION SYSTEM 失效
公开(公告)号：JP2001144627A
公开(公告)日：2001-05-25
申请号：JP32114099
申请日：1999-11-11
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HASHIMOTO YUICHI , SAKAMOTO HIROSHI
IPC分类号： G06F11/10 , G06F12/16 , G11B20/18 , H03M13/15
摘要： PROBLEM TO BE SOLVED: To provide an error correction system that is equipped with a means that individually instructs many syndrome arithmetic units connected in parallel with a bus as to whether or not data received from the bus are to be processed while taking care about arrangement of the data in a CD-ROM. SOLUTION: The four syndrome arithmetic units are connected in parallel with the bus, control lines are placed between each of the syndrome arithmetic units and a DMA controller, and the DMA controller instructs each of the syndrome arithmetic units to accept or disregard transfer data so as to attain simultaneous transfer of data in 4-bytes to a DRAM thereby attaining high-speed transfer and high-speed arithmetic processing.

9. 发明专利

JPH11296471A DATA TRANSFER METHOD AND DMA CONTROLLER 失效
公开(公告)号：JPH11296471A
公开(公告)日：1999-10-29
申请号：JP9747198
申请日：1998-04-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HASHIMOTO YUICHI , KAKIAGE TORU
IPC分类号： G06F13/28
摘要： PROBLEM TO BE SOLVED: To improve transfer efficiency without increasing time required for transfer setting by setting transfer for the transfer of data following data during transfer in a DMA controller while data is transferred. SOLUTION: Transfer setting for transferring data following data during transfer is executed in a DMA controller 100 while data is transferred. A control part 30 sets a storage enable flag 21 so that it cannot be stored when a setting value is stored in the first stage 11 of a queue 10 and sets it so that it can be stored when the value is not stored. When the setting value is stored in a second stage 12, a storage enable flag 22 is set so that it cannot be stored and it is set so that it can be stored when the value is not stored. When the storage enable flag 21 shows that it can be stored, a program can set transfer in the DMA controller 100 through a bus 403. Thus, the program can newly set transfer in the queue 10 even if a transfer execution part 40 is in the middle of transfer by installing the queue 10.

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