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    • 1. 发明专利
    • PLL CIRCUIT MODULE
    • JPH08251045A
    • 1996-09-27
    • JP5535595
    • 1995-03-15
    • MURATA MANUFACTURING CO
    • SAKAI MASARUUNO MASAOHATA TOSHIO
    • H03L7/18H04B1/04H04B1/10H04B1/50
    • PURPOSE: To suppress mutual interference between oscillation systems of a PLL circuit for transmission and a PLL circuit for reception and to reduce interfering to the oscillation system when a signal is amplified. CONSTITUTION: The PLL circuit 10 for transmission which outputs an oscillation signal Ha of frequency 1/n (n>=2) time as high as the sent signal Sa, a multiplying circuit 1 which multiplies the oscillation signal Ha by (n), and the PLL circuit 20 for reception which outputs a signal Src for reception processing are constituted on the same substrate. The sent signal Sa outputted from the multiplying circuit 1 is amplified by an external power amplifier PA and fed to an antenna. Consequently, the mutual interference between the oscillation systems can be suppressed, which is suitable to size reduction. Deterioration in phase noise characteristics due to interference and fluctuations can be prevented. Specially, this module is useful as a PLL circuit module used for a portable telephone set and a mobile object communication equipment.
    • 3. 发明专利
    • VOLTAGE-CONTROLLED OSCILLATOR AND ITS PRODUCTION
    • JPH10284935A
    • 1998-10-23
    • JP9080497
    • 1997-04-09
    • MURATA MANUFACTURING CO
    • SAKAI MASARU
    • H05K9/00H01L23/12H01L23/498H01L23/50H03B1/00H03B5/02H05K1/02H05K3/40
    • PROBLEM TO BE SOLVED: To secure distance between input/output terminals and to prevent the deterioration of a phase noise(C/N) characteristic by permitting terminals formed in recessed parts which are arranged in the corner parts of a substrate to be an input terminal or an output terminal. SOLUTION: A varicap diode VD, transistors Tr1 and Tr2, a capacitor C and bypass capacitors BC1 and BC2, etc., are provided on the main surface 2a of the substrate. The recessed parts 4a, 4b, 4c and 4d are formed in the corner parts of the substrate 2, a conductor is applied on respective inner peripheral surfaces and a power voltage terminal Bv, a voltage control input terminal VC, a modulation terminal M and the output terminal P are formed. The recessed parts 5a, 5b, 5c and 5d with an opening being wider than that of the recessed parts 4a-4c are formed in the almost center part of the side surfaces 2c, 2d, 2e and 2f on the substrate 2, the conductor is applied on the respective inner peripheral surfaces and grounded terminals G1, G2, G3 and G4 are formed. Thus, the dimension of the length of a substrate diagonal line is secured between the input terminal VC and the output terminal P.