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1. 发明专利

JPH1138936A DISPLAY DEVICE 失效
公开(公告)号：JPH1138936A
公开(公告)日：1999-02-12
申请号：JP19108997
申请日：1997-07-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHINOHARA HIROSHI , OONAWA TOSHIO , TERASAWA TAKESHI , NISHIMURA MASARU
IPC分类号： G02F1/133 , G09G3/36
摘要： PROBLEM TO BE SOLVED: To provide a display device that can enhance convenience of users and that is small in dispersion of optical characteristics by making the gradation-vs.-luminance characteristic to be adjustable. SOLUTION: The device is provided with a gradation converting circuit 6, which includes a pixel circuit 1 of matrix arrangement that generates brightness in accordance with the gradation signal supplied from a row driving circuit 2 and converts the gradation of first image data inputted externally by a variable conversion characteristic to obtain a second image data. The row driving circuit 2 supplies gradation signals to the pixel circuit 1 using the second image data converted by this gradation converting circuit 6.

2. 发明专利

JP2523736B2 失效
公开(公告)号：JP2523736B2
公开(公告)日：1996-08-14
申请号：JP32794087
申请日：1987-12-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： KUMANOTANI MASAKI , SHINOHARA HIROSHI , DOSAKA KATSUMI , KONISHI YASUHIRO , KOMATSU TAKAHIRO , YAMAZAKI HIROYUKI
IPC分类号： G11C11/409 , G11C11/34

3. 发明专利

JPH05326796A SEMICONDUCTOR DEVICE PACKAGE 失效
公开(公告)号：JPH05326796A
公开(公告)日：1993-12-10
申请号：JP15585492
申请日：1992-05-21
申请人： MITSUBISHI ELECTRIC CORP
发明人： SATO HISAYASU , SHINOHARA HIROSHI
IPC分类号： H01L23/50
摘要： PURPOSE:To enable a semiconductor device sealed up in a package to be enhanced in heat dissipating effect by a method wherein leads are composed of two or more kinds of leads different at least in width or thickness. CONSTITUTION:A semiconductor device is sealed up in a four-direction flat package, where leads 3 are provided as usual and furthermore leads 6 wider than the leads 3 are provided. The leads 3 and 6 are connected to the semiconductor device inside the sealing material through the intermediary of metal fine wires. As the wide leads 6 come into contact with the semiconductor device wide in contact area, heat released from the semiconductor device can be efficiently dissipated through the leads 6. Moreover, if the wide leads 6 are used as power feeding leads, the leads 6 are small in voltage drop caused by a power supply current, so that the semiconductor device can be stably operated.

4. 发明专利

JPH0529313A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0529313A
公开(公告)日：1993-02-05
申请号：JP18457791
申请日：1991-07-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUMOTO TAKASHI , TSUJIHASHI YOSHIKI , SHINOHARA HIROSHI
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To provide a semiconductor integarted circuit device wherein it is possible to prevent disconnection of metal wining and its yield and its reliability are enhanced. CONSTITUTION:The length of transistor upper wining 16 on transistor upper wining tracks 104 is made shorter than the length of transistor outer wining 107 on transistor outer wining tracks 105. Thereby, the length of the transistor upper wining 106 in which the probability to cause a disconnection or the like is higher than that of the transistor outer wining 107 is made shorter than that in conventional ones. As a result, the probability to cause a defect in all the wining between cells is reduced, and the yield and the reiliability of the title circuit device can be enhanced.

5. 发明专利

JPH0453037B2 失效
公开(公告)号：JPH0453037B2
公开(公告)日：1992-08-25
申请号：JP13020485
申请日：1985-06-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： ICHINOSE KATSUKI , SHINOHARA HIROSHI
IPC分类号： H01L27/10 , G11C11/34 , G11C11/409 , G11C11/413 , G11C11/417

6. 发明专利

JPH0421957B2 失效
公开(公告)号：JPH0421957B2
公开(公告)日：1992-04-14
申请号：JP29706286
申请日：1986-12-12
申请人： MITSUBISHI ELECTRIC CORP
发明人： ANAMI KENJI , YOSHIMOTO MASAHIKO , SHINOHARA HIROSHI , TOMIZAWA OSAMU
IPC分类号： G11C11/41 , G11C11/34 , G11C11/413 , G11C11/417

7. 发明专利

JPH03256296A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH03256296A
公开(公告)日：1991-11-14
申请号：JP5686490
申请日：1990-03-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： MATSUMOTO NORIMASA , SHINOHARA HIROSHI
IPC分类号： G11C11/419
摘要： PURPOSE:To stabilize operation extending over a wide range by impressing always supply potential to the gate electrode of an N-channel type transistor (TR) inserted in series between the source electrode of a P-channel type TR and power supply. CONSTITUTION:The N-channel type TR 8 is inserted between the power supply VDD and the source electrode of the P-channel type TR 9 to constitute a CMOS inverting amplifier 11 for data sense. Here, the supply potential VCC is impressed to the gate electrode of the TR 8, and the source potential of the TR 9 is lowered. Then, the ratio of the channel widths of the TR 9 and the N-channel type TR 10 can be set nearly the same as a usual inverting amplifier. Then, the stable operation can be realized extending over a wide supply voltage range and a wide wafer process parameter range.

8. 发明专利

JPH03231515A PROGRAMMABLE LOGIC DEVICE 失效
公开(公告)号：JPH03231515A
公开(公告)日：1991-10-15
申请号：JP2660390
申请日：1990-02-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHINOHARA HIROSHI
IPC分类号： H03K19/177
摘要： PURPOSE:To attain high speed operation by generating a 2nd clock signal in response to a clock signal from a clock signal generating means and the output of a dummy input line driving means and precharging a 2nd output line to a 1st reference level in response to the 2nd clock signal. CONSTITUTION:Output signal lines on an AND plane 2b and an OR plane 4b are grouped by selecting two lines as a pair and reference potential signal lines CD1, CD2 are disposed in common to the two output signal lines in pairs. Moreover, a clock signal CLKOR for OR plane precharge control is generated in response to the signal potential of input signal lines ADB1, ADB2 of a dummy OR circuit 10 and a clock signal from an AND plane precharge control clock generating circuit 3b. Thus, the precharge/evaluation operation of the OR plane 4b is controlled in the optimum timing at all times and high speed operation is attained without generating a DC through-current in an output buffer without generating a malfunction.

9. 发明专利

JPH0377324A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0377324A
公开(公告)日：1991-04-02
申请号：JP21364389
申请日：1989-08-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： SHINOHARA HIROSHI , KISHI YOSHIYUKI
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To increase resistance to electromigration, to make wiring region small and to realize a high integration by a method wherein a semiconductor integrated circuit is provided with a plurality of metal wirings layers and a plurality of wiring lines and the metal wiring are piled up in parallel on the same wiring lines over a plurality of layers and connected to each other via through-holes. CONSTITUTION:Al metal wiring such as power-supply lines 7a, 8a, signal conductors 7b, 8b, grounding conductors 7c, 8c, and the like are piled up in parallel on the same wirings lines over two layers in a semiconductor integrated circuit substrate which is provided with a plurality of metal wiring layers and a plurality of wiring lines; they are connected to each other via through-holes 6. Widths of the Al wirings 7a, 7b, 7c, 8a, 8b, 8c are narrow as compared with those of conventional metal wirings. The widths of the metal wirings are not made wider but are composed of a plurality of layers. Thereby, an electric current is distributed and a current density is suppressed. Since the widths of the wirings are narrow, the area of the semiconductor integrated circuit becomes small, compared with that of conventional circuits.

10. 发明专利

JPH036598B2 失效
公开(公告)号：JPH036598B2
公开(公告)日：1991-01-30
申请号：JP7236188
申请日：1988-03-26
申请人： MITSUBISHI ELECTRIC CORP
发明人： ANAMI KENJI , YOSHIMOTO MASAHIKO , SHINOHARA HIROSHI , TOMIZAWA OSAMU
IPC分类号： G11C11/41 , G11C11/34

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