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1. 发明专利

JP2561086B2 失效
公开(公告)号：JP2561086B2
公开(公告)日：1996-12-04
申请号：JP8912187
申请日：1987-04-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： ISHIZAKI OSAMU , ICHINOSE KATSUKI
IPC分类号： G11C11/41 , G11C11/34 , G11C11/413

2. 发明专利

JPH0340294A STATIC SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0340294A
公开(公告)日：1991-02-21
申请号：JP17487689
申请日：1989-07-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： ICHINOSE KATSUKI , WADA TOMOHISA
IPC分类号： G11C11/412
摘要： PURPOSE:To reduce energy consumption at standby time, to stably hold data at the time of non-selection and to secure the stability of a memory cell at the time of selection by specifying turning-OFF resistance values to first and second transistors and turning-OFF resistance values to third and fourth transistors. CONSTITUTION:The threshold value voltages of respective first and second transistors 1 and 2 are set high so that a turning-OFF resistance value Rd of the transistors 1 and 2 is larger than a resistance value Rl of first and second loading elements 5 and 6. The threshold value voltages of third and fourth transistors 3 and 4 are set lower than those of the first and second transistors 1 and 2 so that a turning-OFF resistance value Ra for the third and fourth transistors 3 and 4 for access can be larger than the resistance value Rl of the first and second loading elements 5 and 6 and is smaller than the turning- OFF resistance value Rd of the first and second transistors 1 and 2. Thus, when the memory cell is not selected, a data holding characteristic is made satisfactory and further, a current is not increased as well even at the standby time. then, a semiconductor memory can be obtained with the satisfactory stability at the time of selection.

3. 发明专利

JPS6196588A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：JPS6196588A
公开(公告)日：1986-05-15
申请号：JP21783684
申请日：1984-10-16
申请人： Mitsubishi Electric Corp
发明人： ICHINOSE KATSUKI , SHINOHARA HIROSHI
IPC分类号： G11C7/00 , G11C8/08
CPC分类号： G11C8/08
摘要： PURPOSE: To suppress a wasteful column electric current and to reduce power consumption by outputting a line selecting signal of the middle electric potential between an electric power source electric potential and an earth electric potential during the writing period.
CONSTITUTION: The main body 3a of a line decoder 3, when a memory cell 1 selected by selecting the electric power source voltage, the middle voltage and the earth voltage from a ternary signal generating circuit 3b is read, written and in other cases, impresses the electric power source voltage, the middle voltage and the earth voltage is a line selecting signal line in accordance with the respective above-mentioned operations. Consequently, comparing with the time when the electric power source voltage is impressed not only at the time of reading but at the time of writing, a column electric potential during the writing period can be decreased, a wasteful column electric current can be suppressed and the power consumption can be decreased.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在写入期间输出电源电位和接地电位之间的中间电位的选线信号，抑制浪费的列电流，降低功耗。构成：线解码器3的主体3a当从三元信号发生电路3b中选择电源电压，中间电压和接地电压而选择的存储单元1被读取时，写入，在其他情况下，电源电压，中间电压和接地电压是根据上述各个操作的线选择信号线。因此，与读取时而在写入时不同时刻施加电源电压的时间相比，可以减少写入期间的列电位，能够抑制浪费的列电流，功耗可以降低。

4. 发明专利

JPH0289293A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH0289293A
公开(公告)日：1990-03-29
申请号：JP14432088
申请日：1988-06-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： ICHINOSE KATSUKI , ANAMI KENJI , WADA TOMOHISA
IPC分类号： G11C11/412 , G11C11/41
摘要： PURPOSE:To strengthen durability against a software error under an operation state by stabilizing the potential of storage node storing the information of a high level at the time of the selection of a memory cell at higher potential than (a word line voltage - the threshold voltage of a transistor element for access). CONSTITUTION:When word lines 16a-16n are selected, the threshold voltage VTHW of the MOSFET 31 of word line drivers 30a-30n and the threshold voltage VTHD of MOSFET 2 and 3 for an inverter are set, or the resistance value R of high load resistances 4 and 5 is suitably set, so that the potential of nodes 8 and 9 to store 'H' level information (High data) may be stabilized at higher potential than (power source potential Vcc - threshold voltage VTH of MOSFET (MOS field effect transistor) T 6 or T 7 for the access). Consequently, the potential decrease of the node to store high level information can be prevented. Thus, the highly reliable semiconductor memory device durable against the software error can be obtained.

5. 发明专利

JPH0262780A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0262780A
公开(公告)日：1990-03-02
申请号：JP21430288
申请日：1988-08-29
申请人： MITSUBISHI ELECTRIC CORP
发明人： ANAMI KENJI , ICHINOSE KATSUKI
IPC分类号： G11C11/401 , G11C7/00 , G11C8/12 , G11C8/14 , G11C11/407 , G11C11/41
摘要： PURPOSE:To reduce memory cell group selection time by using a signal from a main row selection line and a large memory cell group selection line so as to select a sub row selection line and using a signal from a sub row selection line and a small memory cell group selection line so as to select a split word line. CONSTITUTION:A main global decoder 631 selects a main row selection line 661 and a sub global decoder 6411 receiving a signal from the main row selection line 661 and a large memory cell group selection line 701 selects a sub row selection line 6711. Moreover, a local decoder 6511 receiving a signal from the sub row selection line 6711 and a small memory cell group selection line 711 is used to select a split word line 6811. Thus, the number of stages of decode function gates is increased by one stage and the delay is caused by the increase, but since the total load gate number driven in one cycle is reduced, the time selecting the memory cell is reduced.

6. 发明专利

JPH01161908A DIFFERENTIAL AMPLIFIER 失效
公开(公告)号：JPH01161908A
公开(公告)日：1989-06-26
申请号：JP32210587
申请日：1987-12-17
申请人： MITSUBISHI ELECTRIC CORP
发明人： ICHINOSE KATSUKI
IPC分类号： H03F3/345 , H03F3/34 , H03F3/347
摘要： PURPOSE:To obtain a high voltage gain in a wide range of an average level of an input signal by using 7th and 8th transistors(TR) and limiting a current flowing to 5th and 6th TRs if the average potential level of the input signal to 1st and 2nd input terminals is low. CONSTITUTION:The amplifier is provided with the 5th and 6th TRs 9, 10 keeping the voltage gain high by contributing the amplification at a region where if the average potential level of the input signal to the 1st and 2nd input terminals 4, 8 is low, and the 7th and 8th TRs 11, 12 excluding the effect of the 5th and 6th TRs by limiting a current flowing to the 5th and 6th TRs if the average potential level of the input signal to the 1st and 2nd input terminals 4, 8 is low. Thus, a high voltage gain is obtained over a wide range of the average potential level of the input signal to the 1st and 2nd input terminals 4, 8 and a wide operating voltage margin is ensured in the application of the amplifier to, e.g., a sense amplifier.

7. 发明专利

JPS62252592A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS62252592A
公开(公告)日：1987-11-04
申请号：JP9721986
申请日：1986-04-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： ICHINOSE KATSUKI , MURAKAMI SHUJI
IPC分类号： G11C11/41 , G11C11/34 , G11C11/401 , G11C11/403 , G11C11/413
摘要： PURPOSE:To obtain a second address transition detecting pulse in which both edges of a fall and a rise are steep and the pulse width can be correctly controlled by synchronizing and making variable the impedance of the load element of the second address transition detecting circuit to the change of an address. CONSTITUTION:When a load impedance control signal line 24 comes to be an 'L' level, the impedance of a load element 21 comes to be very low, and the second address transition detecting signal line 22 is quickly charged through the load element 21 and comes to be rapidly an 'H' level. Namely, when the second address transition detecting signal line 22 should discharge, the impedance of the load element 21 is highly set and when the line should charge, the impedance of the load element 21 is lowly set. Thus, both the fall and rise of the second address transition detecting pulse 9 are steep, and the pulse width can be correctly controlled by the pulse width of the first address transition detecting pulse 5 and a load impedance control circuit 23.

8. 发明专利

JPS61103223A Constant voltage generating circuit 失效
标题翻译：恒电压发生电路
公开(公告)号：JPS61103223A
公开(公告)日：1986-05-21
申请号：JP22629384
申请日：1984-10-26
申请人： Mitsubishi Electric Corp
发明人： SHINOHARA HIROSHI , ICHINOSE KATSUKI
IPC分类号： G05F3/24
CPC分类号： G05F3/247
摘要： PURPOSE: To set a continuous output voltage and to obtain a stable output voltage by using at least two resistance means to divide the voltage between an output terminal and a reference potential and using this divided voltage to control a pull-down means for the output voltage.
CONSTITUTION: The impedance of resistance R2 and R3 are set at levels much higher than the impedance set in the conduction mode of an FET-T3. Thus the potential VB
1 is defined at a point B
1 as VB
1 =VA-VTHT
3 , where VA and VTHT
3 show the voltage and the threshold voltage at a point A respectively. While the potential VC is shown at a point C as VC=VB
1 .{R2/(R2+R3)}. Here VC=VTHT
2 +α is also satisfied, where α and VTHT
2 show the value showing the conduction degree of FET-T2 and the threshold voltage respectively. Under such conditions, VA=VTHT
3 +[1+{(R2/R3)}.(VTHT
2 +α)] is satisfied. Therefore the output voltage VA depends on R2/R3, and the resistance value can be changed by the geometric form of an element. Thus it is possible to change continuously the set level of the voltage VA without complicating the manufactur ing process.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：设置连续输出电压，并通过使用至少两个电阻装置来获得稳定的输出电压，以分压输出端子和参考电位之间的电压，并使用该分压来控制输出电压的下拉装置。构成：电阻R2和R3的阻抗设置在比FET-T3的导通模式下设置的阻抗高得多的水平。因此，电位VB1在点B1处被定义为VB1 = VA-VTHT3，其中VA和VTHT3分别表示A点处的电压和阈值电压。而电位VC显示在VC = VB1的位置。{R2 /（R2 + R3）}。此处，VC = VTHT2 +α也满足，其中α和VTHT2分别示出了显示FET-T2的导通程度和阈值电压的值。在这种条件下，VA = VTHT3 + [1 + {（R2 / R3）}。（VTHT2 +α）]。因此，输出电压VA取决于R2 / R3，电阻值可以通过元件的几何形式改变。因此，可以连续地改变电压VA的设定水平，而不会使制造过程复杂化。

9. 发明专利

JPS6098666A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6098666A
公开(公告)日：1985-06-01
申请号：JP20695983
申请日：1983-11-02
申请人： MITSUBISHI ELECTRIC CORP
发明人： ICHINOSE KATSUKI
IPC分类号： H01L29/78 , H01L21/76 , H01L27/10
摘要： PURPOSE:To form the titled device having no influence of bird's beaks by a method wherein element isolation is constructed by a MOS transistor with a poly Si layer or the like as the gate electrode. CONSTITUTION:The MOS type memory device constructed by forming diffused regions 13, a gate oxide film 15, and the poly Si layer 14 on a substrate 11 is provided with an isolating section A in order to isolate from an adjacent element. This section A has the poly Si layer 12 serving as the gate electrode of a MOS transistor. The layer 12 is biased at the ground potential and electrically isolates each transistor.

10. 发明专利

JPH0471365B2 失效
公开(公告)号：JPH0471365B2
公开(公告)日：1992-11-13
申请号：JP257986
申请日：1986-01-08
申请人： MITSUBISHI ELECTRIC CORP
发明人： MURAKAMI SHUJI , ICHINOSE KATSUKI
IPC分类号： H03F3/345 , H03F3/45 , H03K19/0952

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