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1. 发明专利

JP2003332454A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003332454A
公开(公告)日：2003-11-21
申请号：JP2002143278
申请日：2002-05-17
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KAWASHIMA HIKARI , IGARASHI MOTOSHIGE , HIGASHIYA KEIICHI
IPC分类号： H01L27/04 , H01L21/02 , H01L21/265 , H01L21/324 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L27/088 , H01L29/78
CPC分类号： H01L28/20 , H01L21/26513 , H01L21/324 , H01L27/0629
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a semiconductor device, forming conductive silicon films of a predetermined pattern which are provided with a required resistance value. SOLUTION: Heat treatment for activating impurities in respective polycrystalline silicon films, which become gate electrodes 3a and resistance elements 3b, is effected under a condition that respective polycrystalline silicon films are coated with an oxide film 7 after implanting the impurities into the polycrystalline silicon films respectively. In this case, the concentration of impurities in respective polycrystalline silicon films is regulated by controlling the thickness of the oxide film 7. According to this method, the degree of activation of the impurities is regulated. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：为了提供半导体器件的制造方法，形成具有所需电阻值的预定图案的导电硅膜。解决方案：在成为栅电极3a和电阻元件3b的各个多晶硅膜中激活杂质的热处理是在各种多晶硅膜在将杂质注入多晶中后用氧化物膜7涂覆的条件下进行的硅膜。在这种情况下，通过控制氧化膜7的厚度来调节各多晶硅膜中的杂质浓度。根据该方法，调节杂质的活化程度。版权所有（C）2004，JPO

2. 发明专利

JPH1167927A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH1167927A
公开(公告)日：1999-03-09
申请号：JP24424597
申请日：1997-09-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： YOSHIYAMA KENJI , IGARASHI MOTOSHIGE , YAMADA KEIICHI , OKADA KATSUYA , HIGASHIYA KEIICHI
IPC分类号： H01L21/336 , H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To prevent the film quality of a gate insulating film from deteriorating and prevent deterioration of electric characteristics, by forming an oxidation preventing film that prevents gate electrode oxidation on the side plane of either a first or second gate electrode. SOLUTION: On the side plane of a second gate electrode 19, a side wall nitride film 21 which operates as a oxidation preventing film that prevents the second gate electrode 19 from oxidizing is formed. In the subsequent process under the condition that the side wall nitride film 21 is formed on the side plane of the second gate electrode 19, a nitriding process for forming a first field effect transistor insulating film 6 is performed. Therefore, the lower side plane of the second gate electrode 19 is prevented from oxidizing and generation of gate bird's beak can be prevented. As a result, deterioration of the gate insulating film quality is prevented, and the electric characteristics of a semiconductor device provided with a plurality of field effect transistors are prevented from deteriorating.

3. 发明专利

JPH053189A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH053189A
公开(公告)日：1993-01-08
申请号：JP15188791
申请日：1991-06-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： HIGASHIYA KEIICHI
IPC分类号： H01L21/316
摘要： PURPOSE:To enable a gate bird's beak generated at the time when an oxide film which contains boron and phosphorus is made to reflow at a low temperature to be reduced to a minimum. CONSTITUTION:A polysilicon layer or an amorphous silicon layer 101 is formed on the surface of a semiconductor substrate 1 where a transistor and others are formed. An oxide film 12 which contains baron and phosphorus is formed on the surface of the polycrystalline silicon layer or the amorphous silicon layer 101. The oxide film 12 which contains boron and phosphorus is oxidized through a wet oxidation method to be flattened.

4. 发明专利

JPH04360570A LAMINATED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04360570A
公开(公告)日：1992-12-14
申请号：JP16395191
申请日：1991-06-06
申请人： MITSUBISHI ELECTRIC CORP
发明人： TANIZAWA MOTOAKI , HIGASHIYA KEIICHI
IPC分类号： H01L27/00
摘要： PURPOSE:To easily connect adjacent circuits to each other through openings for wiring and, at the same time, to prevent unnecessary crosstalk of signals between each layer of a semiconductor circuit by providing the openings through conductor layers in insulator films between each layer of the semiconductor circuits. CONSTITUTION:Stripe-like conductors 1-6 which are respectively composed of two layers are arranged in layer insulating films 18 which separate the first to fourth layer circuits 20-23 of a semiconductor circuit from each other. The wiring 17 of each layer is connected to the conductors 1-6 and the circuit wiring 17 of each layer is connected to the circuit wiring 17 of its adjacent layer by means of wiring passed through gaps (openings) between each conductor 1-6. Since the shield layers for preventing crosstalk are formed to a stripe-like shape in such a way, each adjacent circuits can be connected to each other without passing through earthing or power supply wires. In addition, since the stripe-like conductors 1-6 can be set to different potentials and can be used as wires for earthing and power supply potential, the degree of wiring freedom can be increased.

5. 发明专利

JPH0439960A BI-MOS SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0439960A
公开(公告)日：1992-02-10
申请号：JP14821490
申请日：1990-06-05
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMASHITA YUKIHIRO , HIGASHIYA KEIICHI
IPC分类号： H01L27/06 , H01B3/22 , H01L21/8249
摘要： PURPOSE:To suppress the performance degradation of a semiconductor device, such as a decrease in cutoff frequency, by forming a bipolar transistor at a lower level. than an NMOS transistor to make narrow the effective collector region of the bipolar transistor. CONSTITUTION:An npn bipolar transistor 100, a PMOS transistor 200, and an NMOS transistor 300 are formed on a semiconductor substrate 1. A step is formed on the border between an n-well region 7b of the transistor 200 and a p-well region 5 of the transistor 300, so that the bipolar region A can be formed at a lower level than the NMOS transistor 300 that is formed in the MOS transistor region B. As a result, the effective collector region of the bipolar transistor is narrow, and the performance degradation, such as a decrease in cutoff frequency, is suppressed.

6. 发明专利

JPH01169940A ELEMENT ISOLATION STRUCTURE AND ITS MANUFACTURE 失效
公开(公告)号：JPH01169940A
公开(公告)日：1989-07-05
申请号：JP33266687
申请日：1987-12-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： OKADA KATSUYA , HIGASHIYA KEIICHI
IPC分类号： H01L21/76
摘要： PURPOSE:To obtain an element isolation structure suitable for high density integration, by a method wherein a protruding insulator is formed on the main surface of a substrate, a semiconductor layer is formed on the substrate so as to be in contact with said insulator, and the semiconductor layer is turned into an active region. CONSTITUTION:On the main surface of a Si substrate 1, a nitride film 2 is formed thick, and subjected to patterning by photoengraving art. An oxide film 3 having a specified thickness is formed on the whole substrate surface, and an oxide film 4 on the nitride film 2 side part only is left by anisotropic etching of RIE and the like. Then, the nitride film 2 is etched and eliminated. A single crystal Si layer 5 is formed by selective epitaxy, and this Si layer 5 is used as an active layer. Then, an isolation structure is obtained wherein the thickness effective in element isolation is large. Further, there is no bird's beak, so that the active region is not narrowed and the structure is made suitable for high density integration.

7. 发明专利

JPS6455840A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6455840A
公开(公告)日：1989-03-02
申请号：JP21330587
申请日：1987-08-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： HIGASHIYA KEIICHI
IPC分类号： H01L21/205 , H01L21/76 , H01L29/78
摘要： PURPOSE:To reduce positive fixed charge amount generated in an oxide film when an ionizing radioactive ray is incident by isolating elements by a polycrystalline silicon enclosed with a thin oxide film. CONSTITUTION:A thin oxide film 2 is formed on a P-type silicon substrate or a P-type well 1, and a polycrystalline silicon 3 is formed thereon. The silicon 3 employs that doped with phosphorus. Then, the isolating width is patterned, and only the silicon 3 is enclosed with a thin oxide film 4. Thereafter, an active region 5 made of a silicon epitaxial layer is formed by selectively epitaxial growth. Subsequently, an N type diffused layer 8, a gate oxide film 6 and a gate electrode 7 are formed on the region 5. Thus, elements are isolated by the polycrystalline silicon enclosed with the film 4 to remarkably reduce the positive fixed charge amount generated at the film 4 as compared with a conventional case.

8. 发明专利

JPS63177471A MOS-TYPE SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63177471A
公开(公告)日：1988-07-21
申请号：JP866787
申请日：1987-01-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： HIGASHIYA KEIICHI , INOUE YASUAKI
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To enhance the controllability of the effective channel length and to prevent a punch-through phenomenon from occurring at a miniaturized MOS transistor by a method wherein a source-drain region is formed on a semiconductor substrate and only on both side-walls of a gate electrode. CONSTITUTION:A gate insulating film 3 and a gate electrode 4 are formed on one main face of a semiconductor substrate 1; impurity regions 5, 6 whose conductivity type is opposite to that of the semiconductor substrate 1 are formed on the semiconductor substrate 1 and only on both sides of the gate electrode 4. For example, after a gate oxide film 3 and a gate electrode 4 have been formed, an oxide film 7 is coated only on the periphery of the gate electrode 4, and polysilicon is then deposited. This polysilicon film is to contain phosphorus or arsenic. Then, said polysilicon film is left only on the side walls of the gate electrode 4 in the channellength direction by using an etching method or the like; a source 5 and a drain 6 are formed. In addition, impurities are diffused into silicon from the source 5 and the drain 6 during a subsequent heat-treatment process so that shallow junction regions 8, 9 are formed.

9. 发明专利

JP2000353803A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000353803A
公开(公告)日：2000-12-19
申请号：JP16392999
申请日：1999-06-10
申请人： MITSUBISHI ELECTRIC CORP
发明人： YOSHIYAMA KENJI , HIGASHIYA KEIICHI
IPC分类号： H01L23/522 , H01L21/285 , H01L21/334 , H01L21/336 , H01L21/60 , H01L21/768 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which is subminiaturized in size, and a method of manufacturing the same. SOLUTION: A gate electrode 31 is covered with a silicon nitride film 7, which has a larger etching selection ratio than that of an NSG film 14 under prescribed etching conditions. A cobalt silicide film 13 is formed on the top surfaces of source/drain regions 10 and 11. Furthermore, a high-melting metal silicide constituting a gate electrode 312 is formed of a cobalt silicide film 12.

10. 发明专利

JP2000124450A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000124450A
公开(公告)日：2000-04-28
申请号：JP29052898
申请日：1998-10-13
申请人： MITSUBISHI ELECTRIC CORP
发明人： YAMADA KEIICHI , MAEDA ATSUSHI , YOSHIYAMA KENJI , HIGASHIYA KEIICHI
IPC分类号： H01L29/78 , H01L21/336 , H01L21/74 , H01L23/485 , H01L29/417
摘要： PROBLEM TO BE SOLVED: To increase the packing density of a transistor without impairing desired device characteristics. SOLUTION: An N-type source region 16 and an N-type drain region 18 are formed in a P-well 14 functioning as the substrate region of an NMOS transistor. A first contact plug 34 in conduction with the N-type source region 16 and a second contact plug 36 in conduction with the N-type drain region 16 are made. The N-type source region 16 is made so that it develops a short circuit with the P-well 14. The N-type drain region 18 is made so that it does not develop a short circuit with the P-well 14. The N-type source region 16 is made smaller than the N-type drain region 18.

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