专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2002009802A OPTICAL COMMUNICATION SYSTEM 失效
公开(公告)号：JP2002009802A
公开(公告)日：2002-01-11
申请号：JP2000189628
申请日：2000-06-23
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI
IPC分类号： H04B1/74 , H04B3/46 , H04B10/03 , H04B10/032 , H04B10/07 , H04B10/275 , H04L1/22 , H04L12/42 , H04L12/437 , H04L29/14 , H04B10/02
摘要： PROBLEM TO BE SOLVED: To solve a problem in a conventional optical communication system that has a deteriorated channel utilizing efficiency because a communication capacity of an active system per route is M/2, where M is the maximum communication capacity. SOLUTION: A standby line 5 is provided to configure a standby route between node units B1 and A2 not interconnected by communication lines 3, 4, the transmission available maximum communication capacity M is transmitted through the communication lines 3, 4 and the standby line 5 is used on the occurrence of a fault in the communication line 3 or 4 to back up the transmission.

2. 发明专利

JPH02214319A DIGITAL AGC CIRCUIT 失效
公开(公告)号：JPH02214319A
公开(公告)日：1990-08-27
申请号：JP3538989
申请日：1989-02-15
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI
IPC分类号： H03G3/20 , H03G3/30
摘要： PURPOSE:To attain the changeover from the peak AGC mode to the mean AGC mode in a short pull-in time by comparing a digital value of an output signal with a reference voltage for each pulse, outputting the result as a binarizing signal, comparing a present pulse with a preceding pulse so as to select the peak AGC mode and the mean AGC mode. CONSTITUTION:A significant level signal is at '0' with no signal, an up-down counter 7 is reset and when the significant level signal goes to '1', the gain of a variable gain amplifier 1 is decreased by the feedback control with count-up by an output of a digital comparator 11 (Peak AGC mode). Then when an output of an A/D converter 4 is lower than a reference voltage VRD, an output '1' is fed to as RS flip-flop 10 from an adder 13. Thus, the RS flip-flop 10 is set and a selector 6 selects a countup signal of a computing element 5. The up-down counter 7 is controlled with a countup signal and a countdown signal of the computing element 5 (mean value AGC mode). Thus, when the output level reaches the reference level by the peak AGC mode, it is detected immediately and since the mode enters the mean AGC mode, the gain control with a short pull-in time is applied.

3. 发明专利

JPS63136709A DISCRIMINATION FEEDBACK TYPE EQUALIZER 失效
公开(公告)号：JPS63136709A
公开(公告)日：1988-06-08
申请号：JP28262686
申请日：1986-11-27
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI , KUWABARA HIROTO
IPC分类号： H03H15/00 , H04B3/04
摘要： PURPOSE:To equalize an input signal waveform asymmetrical in both polarities completely by converging a positive and a negative filter coefficient by means of the revision arithmetic operation during the training period and using a filter coefficient for the transmission period obtained based on said converged bipolar filter coefficient. CONSTITUTION:A period training signal having a period No with negative/ positive polarities is stored in an input register 2 during the training period at first and inputted to a polarity discrimination device 8 at the same time. Since a 3rd selection circuit 14 selects the training signal, the signal input via an AMI discriminator 1 does not enter the input register but is outputted only. The polarity discriminator 8 discriminates the polarity of the training signal at the period, that is, whether the peak value is 1 or -1 and gives the result to 1st and 2nd selection circuits 11, 13. When the polarity discriminator 8 discriminates the positive polarity, and 2nd selection circuit 13 selects a 1st coefficient register 9 and outputs the data stored therein into a register 5. When the polarity discriminator discriminates the negative polarity, the 2nd selection circuit 13 selects a 2nd coefficient register 10.

4. 发明专利

JPH03211920A LINE EQUALIZER 失效
公开(公告)号：JPH03211920A
公开(公告)日：1991-09-17
申请号：JP678190
申请日：1990-01-16
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI
IPC分类号： H04B3/06
摘要： PURPOSE:To keep a convergence time almost constant and to attain stabilized convergence decision by independently executing peak value control by a flat gain variable circuit, and inter-code interference control by a variable equalizer. CONSTITUTION:The output of a flat gain variable circuit 2 is inputted to a peak value detector 4 and the gain of the flat gain variable circuit 2 is controlled by a direct current amplifier 5. A variable equalizer 3 is set in the rear step of the flat gain variable circuit 2, the output is inputted to an inter-code interference detector 6 and the inter-code interference detector 6 controls the gain of the variable equalizer 3. Thus, since the inter-code interference detector 6 controls the gain after the flat gain variable circuit 2 is convergent, inter-code interference can be made zero without changing a peak value.

5. 发明专利

JPS62235828A VARIABLE EQUALIZER 失效
公开(公告)号：JPS62235828A
公开(公告)日：1987-10-16
申请号：JP7967586
申请日：1986-04-07
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI , IIZUKA IKUO
IPC分类号： H04B3/06 , H04B3/14
摘要： PURPOSE:To obtain the stable result of equalization with high speed and high accuracy by constituting a slope part characteristic equalizing circuit of a transmission line by a digital filter and using gain information from a flat characteristic equalizing circuit as an initial value so as to select optimizingly a fitler coefficient prepared in advance thereby minimizing the inter-code interference. CONSTITUTION:Supposing the output data of an A/D converter 3 are Xt (t=-infinity ,--1,0,1,-), a tap number of a digital filter 5 is N, a set of the i-th tap coefficient is (Ci,jIj=1, 2,-N), an output yt of the digital filter 5 is expressed in equation. The digital filter 5 is the slope part characteristic equalizing circuit of a line, and the set of tap coefficient (Ci, jIj=1,2,-,N) deciding its characteristic is stored in a read only memory 4, while the line is increased in the unit of a prescribed length Lm as to a representative line so as to compensate the characteristic of the line length of li=L X i(m). A route f control circuit 7 selects the set of tap coefficient of the digital filter 5 from read only memories 4 to equalize the slope part characteristic of the line.

6. 发明专利

JPH05235933A 失效
公开(公告)号：JPH05235933A
公开(公告)日：1993-09-10
申请号：JP3184992
申请日：1992-02-19
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI , MAKINO SHINYA , CHIKASAWA TAKESHI , MATSUI MITSURU , SAKURAI KOICHI
IPC分类号： G06F21/20 , G06F15/00 , G09C1/00 , H04L9/32 , H04L12/44
摘要： PURPOSE:To prevent an outgoing transmission signal from a station equipment to a terminal equipment from being intercepted by other terminal equipment by allowing the station equipment to identify the terminal equipment based on a terminal equipment identification ID number allocated fixedly to the user of the terminal equipment. CONSTITUTION:The system is provided with IC cards 51-5n storing a terminal equipment identification ID number allocated fixedly to the user of the terminal equipment, terminal equipments 11-1n reading the ID number from the IC cards 51-5n and sending the number to a station equipment 2, the station equipment 2 identifying the terminal equipments 11-1n based on the received ID number and a branch circuit 3 connecting the terminal equipments 11-1n and the station equipment 2. The terminal equipments 11-1n read the identification ID number allocated fixedly to the user of the terminal equipment stored in the IC cards 51-5n, sends the number to the station equipment 2, and the station equipment 2 identifies the terminal equipment based on the received ID number. Thus, it is not required to designate a time slot position in advance to the terminal equipments 11-1n and a transmission terminal equipment of data on a time slot is specified and the validity is confirmed.

7. 发明专利

JPH0568271A STARTUP SYSTEM IN OPTICAL SUBSCRIBER LINE TRANSMISSION SYSTEM 失效
公开(公告)号：JPH0568271A
公开(公告)日：1993-03-19
申请号：JP12207191
申请日：1991-04-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI
IPC分类号： H04B10/556 , H04B10/00 , H04J3/00 , H04M3/22 , H04Q3/42
摘要： PURPOSE:To avoid the effect onto a reception signal due to a transmission signal between line terminators(LT) by making a burst phase in time division 2-way in a transmission line interface entirely identical. CONSTITUTION:When a network terminator NT2 sends a call signal to a transmission line terminator LT4 via an optical fiber cable in response to a call from a terminal equipment TE1, the transmission line terminator LT4 recognizes the call and sends an optical pulse signal having a constant burst phase to the network terminator NT2 under the control of a subscriber line exchange ET5. Then frame synchronization is taken in the direction of LT NT and NT LT in the transmission line interface and the burst phase of the optical pulse signal in the direction of LT NT is made identical between all LTs NTs under the control of the ET5, resulting in making the burst phase in all the transmission line interfaces identical. Thus, the timing of the transmission reception in each LT4 is entirely identical to each other and the effect on the reception signal by the transmission signal is avoided.

8. 发明专利

JPH03261239A RECEPTION CIRCUIT FOR TIME DIVISION BI-DIRECTIONAL TRANSMITTER 失效
公开(公告)号：JPH03261239A
公开(公告)日：1991-11-21
申请号：JP5947090
申请日：1990-03-09
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI
IPC分类号： H04L5/16
摘要： PURPOSE:To prevent noise caused at switching from transmission to reception state from being amplified by starting the operation of an automatic gain control section of a reception circuit of a time division bi-directional transmitter with a signal retarding a transmission reception control signal. CONSTITUTION:The reception circuit is provided with an automatic gain control section 6 generating a gain control signal in response to a level of an output signal of an input selection amplifier 5 and controlling the gain of a variable gain amplifier 4, and a delay element delaying a transmission reception control signal to control the operation start of the automatic gain control section 6 with an output of the delay element 8. That is, the transmission reception control signal is inputted to the delay element 8 and its output starts the operation of the automatic gain control section 6, then a fact of amplifying a switching noise as a reception signal is avoided. Then the level is adjusted by a gain control signal with respect to a substantial reception signal. Thus, the noise caused from the transmission to the reception is prevented.

9. 发明专利

JPH01170226A DIGITAL CONTROLLED AGC CIRCUIT 失效
公开(公告)号：JPH01170226A
公开(公告)日：1989-07-05
申请号：JP32922387
申请日：1987-12-25
申请人： MITSUBISHI ELECTRIC CORP
发明人： AKITA MASASHI
IPC分类号： H04B3/06
摘要： PURPOSE:To converge an output signal to a desired level accurately in a short time by varying the gain control width of a variable gain amplifier and applying gain control. CONSTITUTION:The circuit has an A/D conversion means 7 converting an output of a variable gain amplifier 1 from an analog signal into a digital signal, a comparison means 8 comparing the converted digital signal with a desired reference level and outputting the result of comparison as a polarity signal, a detection means utilizing the polarity signal to detect the converging state of the signal of a control variable with respect to a reference level and a gain variable means varying the gain of the variable gain amplifier 1 in a control width in response to the detected converging state. Thus, the converging state of the control variable with respect to the reference level of the signal is detected. Then, the change in the gain of the variable gain amplifier is applied by the gain variable means in the control width in response to the converging state. Thus, the output signal level is controlled to a desired level accurately in a short converging time.

10. 发明专利

JPH1127284A PREFERENTIAL MULTIPLEXER OF CELL 失效
公开(公告)号：JPH1127284A
公开(公告)日：1999-01-29
申请号：JP17942997
申请日：1997-07-04
申请人： MITSUBISHI ELECTRIC CORP
发明人： MAKINO SHINYA , AKITA MASASHI , KITAYAMA TADAYOSHI
IPC分类号： H04Q3/00 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To reduce delay due to multiplex for a cell in which no possibility of the cell discard and the delay in a slave device is allowed by preferentially controlling the multiplex for the slave device based on a signal from a residual amount monitor. SOLUTION: The number of residual cells in a buffer 102 is monitored by a residual amount monitoring circuit 116 and the number of the residual cells in the buffer is informed to a master device 11 in the slave device 12. A monitor circuit output signal 117 is received in the master device 11, one of the slave devices 12 to execute polling, for example, 12i is determined and a preferential control result 119 is transmitted to a polling control circuit 110 in a preferential control circuit 118. An individual polling signal 111i is outputted for line slave 12i corresponding to the control result 119 in the polling control circuit 110, the cell in a buffer 102i is read by a reading control circuit 105i, cell flow 106i is transmitted to the master device 11 and the cell flow is received by a cell reception circuit 112 in the slave device 12i.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式