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1. 发明专利

JPH11350763A CLEAN ROOM AND ITS CONSTRUCTION METHOD 失效
公开(公告)号：JPH11350763A
公开(公告)日：1999-12-21
申请号：JP16066998
申请日：1998-06-09
申请人： MATSUSHITA ELECTRONICS CORP
发明人： AOKI NORISHIGE , FUJITA MASAHITO , MITSUI AKIRA , UEDA SEIJI
IPC分类号： E04H5/02 , F24F7/06 , H01L21/02
摘要： PROBLEM TO BE SOLVED: To provide a clean room and its construction method capable of eliminating excess investment, constructing at a low cost and shortening an execution period up to the rise of a facility. SOLUTION: The inside of a building outer shell 3 on a foundation floor part 2 is provided with a ceiling room 8, a disposal room 7 on a floor structural part 4 and an underfloor room 6 under the floor structural part 4. In the clean room clean air flows down from the ceiling room 8 to the underfloor room 6 via the disposal room. In this case, a number of frame-like floor structural bodies 5 are disposed on the foundation floor part 2 in the building outer shell 3 to compose the floor structural part 4, a floor structural body 5a for setting each disposal device 10 easily composes the floor structural part 4 satisfying load resistance and vibration resistant performance required for the disposal device 10 without any excess or shortage by making structure suitable for the setting specifications of the disposal device 10, and the clean room can be constructed in a short execution time and at a low cost.

2. 发明专利

JPH0616542B2 失效
公开(公告)号：JPH0616542B2
公开(公告)日：1994-03-02
申请号：JP15163485
申请日：1985-07-10
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L27/04 , H01L21/822 , H01L29/94

3. 发明专利

JPH03257946A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH03257946A
公开(公告)日：1991-11-18
申请号：JP5718690
申请日：1990-03-08
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/76
摘要： PURPOSE:To prevent the extention of bird's beaks owing to selective oxidation and heighten the integration density of elements, by forming the first impurity diffused layer having a peak density in a shallow position, on a semiconductor substrate surface covered with an insulating film, and by forming the second impurity diffused layer having a peak density in a deep position, in a region not covered with the insulating film. CONSTITUTION:A silicon dioxide film 11 having a film thickness of 0.5mum is formed on a P-type silicon substrate 1, the silicon dioxide film 11 is etched selectively using photoresist 41 as a mask, and boron ions are injected after that. A part of the boron ion implanted layer 12 under a silicon dioxide film 11 has its peak density in a shallow position, and it makes the first impurity diffused layer. A region of the p-type silicon substrate 1 not covered with the silicon dioxide film 11 has a peak density of the boron ion implanted layer 12 in a position deeper than about 1mum, and it makes the second impurity diffused layer. Then after a silicon dioxide film 21 being formed thinly annealing processing is conducted, and the above-mentioned P-type first and second impurity diffused layers are formed by boron ion implantation.

4. 发明专利

JPH02278727A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND FORMING METHOD FOR ELECTRODES THEREOF 失效
公开(公告)号：JPH02278727A
公开(公告)日：1990-11-15
申请号：JP9872689
申请日：1989-04-20
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/28
摘要： PURPOSE:To connect a stable electrode by covering the inner face of a through hole with heat resistant alloy, and filling polycrystalline silicon containing N- type impurity in the hole. CONSTITUTION:A P-well region 2, an N-well region 3 and an element isolating region 4 are formed on a P-type silicon substrate 1, an N type diffused layer 5, a P type diffused layer 6 and an interlayer insulating film 7 are respectively provided in the well regions, through holes 8a, 8b for leading electrodes are respectively opened, a molybdenum silicide layer 9 is deposited to cover the opening and the inside wall, and conductive polycrystalline silicon film 10b is buried in the holes 8a, 8b. The layer 9 and the film 10b are covered with aluminum alloy 11, and connected to form electrodes. Thus, the electrodes can be led stably from the miniature through-holes.

5. 发明专利

JPH0220146B2 失效
公开(公告)号：JPH0220146B2
公开(公告)日：1990-05-08
申请号：JP18529183
申请日：1983-10-03
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L23/52 , H01L21/28 , H01L21/3205 , H01L21/336 , H01L21/768 , H01L23/522

6. 发明专利

JPH02110933A WIRING STRUCTURE AND ITS FORMATION 失效
公开(公告)号：JPH02110933A
公开(公告)日：1990-04-24
申请号：JP26164888
申请日：1988-10-19
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/3205 , H01L23/52
摘要： PURPOSE:To lessen the amount of spontaneous oxide film, which is generated on the surface of the boundary between a polycrystalline silicon film and a diffused layer, in a degree that the oxide film can be ignored and to make it possible to connect stably a polysilicide wiring with the diffused layer and the polycrystalline silicon layer by a method wherein the connection of a wiring of a double structure consisting of the polycrystalline silicon film, a metal silicide film and the like with the impurity diffused layer and the like is performed by the metal silicide film and the like. CONSTITUTION:A wiring layer formed by superposing a third conductive film 5 on a second polycrystalline silicon film 4 having a conductivity is laminated on the main surface of a semiconductor substrate 1 having an impurity diffused layer 2, a first polycrystalline silicon film 7 or a wiring layer formed by superposing a metal silicide film on the film 7 through an insulating film 3, the above layer 2 and the like are connected with the film 5 in an opening part in the film 3 and a wiring structure for leading out an electrode is provided. For example, an element isolation region (a silicon dioxide film) 6, an N diffused layer 2, a silicon dioxide film 3 and a polycrystalline silicon film 4 are formed on a P-type silicon substrate 1. Then, the films 4 and 3 are opened one after another by anisotropic etching using a photoresist as a mask and after the photoresist is removed, a tungsten silicide film 5 is deposited.

7. 发明专利

JPH0226068A MANUFACTURE OF ROM 失效
公开(公告)号：JPH0226068A
公开(公告)日：1990-01-29
申请号：JP17598288
申请日：1988-07-14
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： G11C17/08 , H01L21/8246 , H01L27/112
摘要： PURPOSE:To make miniaturization of ROM possible by performing ion- inplantation into a non-selective region for inverse doping while masking a MOS transistor region of a second gate. CONSTITUTION:An N implantation region 10 is formed by previous ion implantation including the part of a second gate region on a semiconductor substrate 1, while a part of this second region part is inversely doped according to a program cord of a ROM. Accordingly, control of threshold value voltage becomes possible in a self-alignment manner with respect to a first gate electrode. Thereby, miniaturization of the second gate electrode becomes possible so that the ROM of high density and a large capacity can be easily realized.

8. 发明专利

JPS63190357A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63190357A
公开(公告)日：1988-08-05
申请号：JP2305487
申请日：1987-02-02
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/3213
摘要： PURPOSE:To improve the shape of step difference for improving the manufacturing yield of aluminum electrode and the reliability of device by a method wherein, when the aluminum electrode of a semiconductor integrated device in high density and integration is led out, a sidewall is formed on the inner wall of a contact window to be tapered. CONSTITUTION:When an electrode is led out from an element previously formed on the main surface of a semiconductor substrate, a contact window 11 is made on the first insulating film formed on the surface of element and then the second insulating film is deposited. Next, the second insulating film is anisotropically etched leaving a sidewall 4a on the inner wall surface of contact window 11 to make the contact window 11 with tapered inner wall. Besides, a metallic wiring is made on the contact window 11. Furthermore, the shape of inner wall surface of the contact window 11 can be controlled arbitrarily by means of optimizing the film thickness of the second insulating film by optimizing the size and the depth of contact hole 11. Through these procedures, the inner wall of contact window 11 is tapered so that the aliminum electrode may be prevented from being disconnected at the step difference in the tapered part to improve the manufacturing yield and the reliability of device.

9. 发明专利

JPS63181459A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63181459A
公开(公告)日：1988-07-26
申请号：JP1472287
申请日：1987-01-23
申请人： MATSUSHITA ELECTRONICS CORP
发明人： UEDA SEIJI
IPC分类号： H01L21/266 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
摘要： PURPOSE:To simplify a production process and to prevent the sheet resistance of polycrystalline silicon from increasing by a method wherein, while a resist for pattern formation of a CMOS integrated circuit is kept remained, P-type impurities are ion-implanted into a P-channel transistor region and a P diffused region is formed. CONSTITUTION:A low-concentration N diffused region 5 is formed at an n-type well 3 of an N-type silicon substrate 1. Gate oxide films 6a, 6b and a phosphorus-doped polycrystalline silicon film 7 are deposited; the specific sheet resistance is about 40 OMEGA/cm . Then, photoresist masks 21a, 21b are formed by a photo-etching method. A resist pattern 22a is formed on a polycrystalline silicon film 7a, and a photoresist mask 22b is formed on the whole surface of a P-type well region. Then, a P diffused region 11 is formed, e.g., by implanting BF2 . While the photoresist 22a is kept remained, an implantation process is executed; boron does not penetrate into the polycrystalline film 7a; it is possible to prevent the sheet resistance from increasing. Lastly, an electrode 13 is extracted.

10. 发明专利

JPS6388842A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6388842A
公开(公告)日：1988-04-19
申请号：JP23484086
申请日：1986-10-02
申请人： MATSUSHITA ELECTRONICS CORP
发明人： OZAKI HIDETO , SHISHINO MASAFUMI , MAYUMI SHUICHI , UEDA SEIJI
IPC分类号： H01L21/3205
摘要： PURPOSE:To prevent the disconnection of an upper-layer metallic interconnection by forming a lower-layer metallic interconnection, executing light ashing treatment by oxygen plasma, etc., to a side wall surface, executing isotropic etching treatment to the side wall surface as the state in which there is a resist pattern is left as it is, and shaping a chamfering working section at an upper end section. CONSTITUTION:An Al film is shaped through sputtering and evaporation in order to mutually connect semiconductor element regions formed into a semiconductor substrate 1, a predetermined resist pattern 2 is shaped, and a lower-layer metallic interconnection 3 is formed through dry etching. The surface of the semiconductor substrate 1 is etched, and the upper end section of the lower-layer metallic interconnection 3 is removed and chamferred. The resist pattern 2 is gotten rid of, and a coated insulating film 4 is shaped. A CVD layer insulating film 5 is deposited on the surface of the semiconductor substrate 1, and a through-hole 6 is bored to the coated insulating film 4. An upper-layer metallic interconnection 7 is formed through sputtering and evaporation, the formation of the resist pattern and a dry etching process.

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