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1. 发明专利

JPS5859622A SUPPRESSING METHOD OF PULSE SIGNAL 失效
公开(公告)号：JPS5859622A
公开(公告)日：1983-04-08
申请号：JP15764781
申请日：1981-10-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMATANI MAKOTO
IPC分类号： H03K5/1252 , H03K5/00
摘要： PURPOSE:To selectively suppress pulses having widths narrower than a fixed one, by detecting such pulses with a counter and suppressing them. CONSTITUTION:A counter 5 is reset when no inputted pulse exists, but it starts counting of clock pulses inputted into a clock input terminal 6 when pulses are inputted. When the counter 5 is designed to output an overflow signal when it counts clock pulses of a prescribed number, it can be arranged that, when an inputted pulse has a width which is narrower than a prescribed width, the inputted pulse is disregarded. When the width of an inputted pulse is broader than the prescribed width, an NOR gate is closed by the overflow output and inputting of clock pulses is stopped. By using two pieces of delay flip flops 9 and 10, a signal whose rising part for a width of one clock pulse period is synchronized with the clock pulse, is obtained from the overflow output.

2. 发明专利

JPS56160049A MODE CHANGE-OVER CIRCUIT 失效
公开(公告)号：JPS56160049A
公开(公告)日：1981-12-09
申请号：JP6456780
申请日：1980-05-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHIJIMA OSAMU , YAMATANI MAKOTO
IPC分类号： G01R31/26 , H01L21/66 , H01L21/822 , H01L27/04 , H03K19/00
摘要： PURPOSE:To perform integration without providing the terminal for inspection by a method wherein the output terminal having the characteristic of outputting a high level or low level of pulse in an operational mode at a fixed cycle is commonly used in performing the change-over of the inspection mode of LSI and the operational mode. CONSTITUTION:In the mode change-over circuit wherein the change-over is performed on the LSI inspection mode and the operational mode, the output of an AND gate 7 is turned out at low level to the output terminal 5 under the state of actual movement, and the Q output of the D flip-flops 2-4, consisting of a shift resistor 1, is also becomes low level. An OR gate is used, instead of AND gates 2 and 6, when there exists a high level or a fixed cycle of pulse is outputted, and an inverter is jointly used. Under the state of inspection mode, the level of the output terminal 5 is forcedly turned to the high level by the output control signal to be applied to a terminal 6. Through these procedures, the mode change-over is performed without providing an exclusive terminal to the LSI and this contributes for better integration.

3. 发明专利

JPH0319727B2 失效
公开(公告)号：JPH0319727B2
公开(公告)日：1991-03-15
申请号：JP6456880
申请日：1980-05-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHIJIMA OSAMU , YAMATANI MAKOTO
IPC分类号： H03K23/66 , H03K21/00 , H03M1/82

4. 发明专利

JPH0296413A VARIABLE GAIN AMPLIFIER 失效
公开(公告)号：JPH0296413A
公开(公告)日：1990-04-09
申请号：JP24813688
申请日：1988-09-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMATANI MAKOTO
IPC分类号： H03G3/20
摘要： PURPOSE:To realize an automatic gain control with an MOS type integrated circuit and to integrate it onto the same substrate as a micro computer by making variable the feedback quantity of an operational amplifier by changing over a switch by a microcomputer control. CONSTITUTION:For the input of a variable gain amplifier 1, a gain is determined by the control of a microcomputer 4. The output is converted to a direct current voltage with a detector 2 and inputted through an A/D converter to the microcomputer 4. The microcomputer 4 computes in accordance with the digital value, the change value or the control input from the external part, determines the gain and the time control of the response of the amplifier 1 and commands to the amplifier 1. At the amplifier 1, the feedback resistance of an operational amplifier 8 is selected by an MOS analog switch group 5 from a feedback resistor group 6 and the gain is variably adjusted.

5. 发明专利

JPH0459810B2 失效
公开(公告)号：JPH0459810B2
公开(公告)日：1992-09-24
申请号：JP1601582
申请日：1982-02-03
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMATANI MAKOTO , NISHIJIMA OSAMU
IPC分类号： H03L7/10 , H03L7/187

6. 发明专利

JPS617973A Operation mode control circuit of microcomputer, and its using method in microcomputer 失效
标题翻译： MICROCOMPUTER的操作模式控制电路及其在微型计算机中的使用方法
公开(公告)号：JPS617973A
公开(公告)日：1986-01-14
申请号：JP12980984
申请日：1984-06-22
申请人： Matsushita Electric Ind Co Ltd
发明人： MIYAZAKI MASAYA , SUZUKI TOSHIAKI , SAKAO TAKASHI , YAMATANI MAKOTO
IPC分类号： G06F15/78
摘要： PURPOSE: To increase an operation mode without providing a complicated external circuit by providing the first and the second terminals for indicating the operation mode, using the former as a bi-directional terminal for outputting an input and a clock signal, and using the latter as an input exclusive terminal.
CONSTITUTION: Terminals 26, 27 are terminals for designating an operation mode. When a clock pulse CPO is an H level, an output of a gate 28 becomes an L level, a P channel MOS transistor 29 turns on, an N channel MOS transistor 30 turns off, and an H level is outputted to the terminal 26. Accordingly, when the clock pulse CPO falls, an input x
1 is latched by an FF31 and an output y
1 becomes an H level. In this case, the terminal 27 is pulled down, and as for an input x
2 of FFs 32, 33, an output y
2 of the FF32 which latches x
2 when the CPO falls becomes an L level, and an output y
3 of the FF33 which latches x
2 when a CP1 falls becomes an L level. By assigning these y
1 , y
2 and y
3 to the operation mode, an operation mode control decoder 8 generates a control signal required for a single chip mode.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过提供用于指示操作模式的第一和第二终端来提供操作模式而不提供复杂的外部电路，使用前者作为用于输出输入和时钟信号的双向终端，并且使用后者作为输入专用终端。构成：端子26,27是用于指定操作模式的端子。当时钟脉冲CPO为H电平时，门28的输出变为L电平，P沟道MOS晶体管29导通，N沟道MOS晶体管30截止，H电平输出到端子26。因此，当时钟脉冲CPO下降时，输入x1被FF31锁存，输出y1成为H电平。在这种情况下，端子27被下拉，并且对于FF32,33的输入x 2，当CPO下降时锁存x2的FF32的输出y2变为L电平，并且输出y3 当CP1下降时锁存x2的FF33成为L电平。通过将这些y1，y2和y3分配给操作模式，操作模式控制解码器8产生单芯片模式所需的控制信号。

7. 发明专利

JPS58133042A PLL CIRCUIT 失效
公开(公告)号：JPS58133042A
公开(公告)日：1983-08-08
申请号：JP1601582
申请日：1982-02-03
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMATANI MAKOTO , NISHIJIMA OSAMU
IPC分类号： H03L7/10 , H03L7/187
摘要： PURPOSE:To eliminate the need to provide a special circuit countermeasure to an LPF, by detecting digitally a non-locking state and then carrying out an operation to reset the non-locking state to a locking state on the basis of the result of the above-mentioned detection. CONSTITUTION:When a circuit system is not locked, a pulse of H level is produced to only one of two output terminals of a phase comparator 4. This pulse is detected by a D-FF10 or 11 and latched by RS-FF12 and 13 respectively. A control circuit 9 feeds an OR signal 17 of the FF12 and 13 switches multiplexers 15 and 16 to a set state after setting an RS-FF14 in a non-locking mode. In this case, the output of an inverter 22 is set at L level for a fixed period of time, and OR gates 20 and 21 are cut off. Under such conditions, the input of an output circuit 5 is connected to outputs Q and Q' of the FF13. At the same time, the output voltage of an LPF6 changes if the FF14 is set, and the frequency of a voltage control ocillator 7 also changes. Then a normal PLL circuit state is reset after the frequency of the oscillator 7 passes through a desired level.

8. 发明专利

JPS56160140A COUNTING CIRCUIT 失效
公开(公告)号：JPS56160140A
公开(公告)日：1981-12-09
申请号：JP6456880
申请日：1980-05-14
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHIJIMA OSAMU , YAMATANI MAKOTO
IPC分类号： H03K23/66 , H03K21/00 , H03M1/82
摘要： PURPOSE:To increase the accuracy without increasing the number of bits at a D/A converter part, by supplying the output of a counting circuit to a delaying circuit part and extracting the prescribed output of a delaying FF circuit via a gate circuit. CONSTITUTION:The output of a counting circuit is supplied to a delaying circuit part formed by giving a cascade connection among delaying FF circuits 11-14 that work by a clock input. At the same time, the prescribed output of the delaying FF circuit is extracted via gate circuit parts 15-17. In this case, the digital data X1 and X0 are (10) each and the output Q3 is produced only at the output terminal of an AND gate circuit 16 to which no data X0 is supplied. Thus signals Q1 and Q3 are applied to an OR gate 20, and the input D of a delaying FF20 is shown as D= Q1VQ3. Then D/Aout is delivered to a terminal 22. This D/A output is filtered through a low-pass filter to carry out a D/A conversion of 12 bits.

9. 发明专利

JPS5687917A ADJUSTER OF TUNING VOLTAGE 失效
公开(公告)号：JPS5687917A
公开(公告)日：1981-07-17
申请号：JP16507179
申请日：1979-12-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HOSOKAWA TAKUHISA , UEDA MINORU , KAWASHIMA KAZUMI , TAKUHARA SADAHIRO , YAMAMOTO HIROSUKE , YAMATANI MAKOTO
IPC分类号： H03J5/02 , H03J7/24 , H03J7/28
摘要： PURPOSE:To enable to make short the time when both voltages are in coincidence by increasing the count speed of a counter at the change-over to the preset mode, by the constitution that one clock pulse can equivalently be used as a plurality of clock pulses. CONSTITUTION:When a switch 13 is switched from the normal mode to the preset mode, the location applying clock pulse to the counter 2 is moved to the input terminal of high rank digit in the counter 2, and the counting is made by further increasing the weight than original clock pulse. One clock pulse generated at the clock pulse generating circuit 1 can equivalently be used as a plurality of clock pulses.

10. 发明专利

JPH0258805B2 失效
公开(公告)号：JPH0258805B2
公开(公告)日：1990-12-10
申请号：JP16507179
申请日：1979-12-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HOSOKAWA HIROHISA , UEDA MINORU , KAWASHIMA KAZUMI , TAKUHARA SADAHIRO , YAMAMOTO HIROSUKE , YAMATANI MAKOTO
IPC分类号： H03J5/02 , H03J7/24 , H03J7/28

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