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3. 发明专利

JPS61180999A DYNAMIC ROM CIRCUIT 失效
公开(公告)号：JPS61180999A
公开(公告)日：1986-08-13
申请号：JP2123785
申请日：1985-02-06
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： OBARA KAZUTAKA , NISHIJIMA OSAMU
IPC分类号： G11C17/12 , G11C17/00
摘要： PURPOSE:To attain a high-speed reading cycle by providing two MOS transistors MOS TR and therefore lowering the level of the gate voltage of a bit line precharging MOS TR and then the level of the precharging voltage of the bit line respectively. CONSTITUTION:The gate and the drain of a MOS TR 12 are connected to a signal line connected to the gate of a precharging MOS TR 5 of a bit line 3. The source of the TR 12 is connected to the gate and the drain of a MOS TR 13, and the source of the TR 13 is grounded. The voltage of an H level of the signal line connected to gate of the TR 5 is lowered. Then the level of the bit line precharging voltage is reduced to reduce the reading cycle time of a dynamic ROM which is decided by the time during which the bit line voltage is reduced down to an input switching level of a MOS circuit connected to the bit line from the precharging voltage level.

6. 发明专利

JPS56166555A CONTROLLING CIRCUIT 失效
公开(公告)号：JPS56166555A
公开(公告)日：1981-12-21
申请号：JP6939580
申请日：1980-05-23
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHIJIMA OSAMU , OOTA KIYOTO
IPC分类号： G06F11/30 , G06F9/40 , G06F9/42 , G06F11/00
摘要： PURPOSE:To escape from an infinite loop, by loading a constant address to a program counter when the counting value of a counter reaches a prescribed value in the controlling circuit where the control of the microcomputer system is executed. CONSTITUTION:A return counter 6 is added which is counted up by 1 by the return instruction from a subroutine and is cleared by the call instruction, and a constant address is loaded to a program counter 2 by the output Cout which is generated when the counting value of the counter 6 reaches a prescribed value, and the execution of a program is started from the loaded constant address. Consequently, when a controlling circuit enters an infinite loop, contents of the return counter 6 reach a prescribed value, and the constant address is loaded to the program counter 2 on the basis of the detection of this prescribed value, and an error processing routine is executed to escape from the infinite loop.

7. 发明专利

JPS54144852A DELAY CIRCUIT 失效
公开(公告)号：JPS54144852A
公开(公告)日：1979-11-12
申请号：JP5334278
申请日：1978-05-04
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： NISHIJIMA OSAMU
IPC分类号： H03H11/26 , H03K5/13
摘要： PURPOSE:To obtain the delay time specified independently of the variation in the power supply voltage, by constituting the delay circuit with the depletion MOS (DMOS) as the load resistive element, three enhancement MOS(EMOS), resistors and capacitors. CONSTITUTION:When the switch 3 is turned off at time t0, the gate voltage V1 of EMOS 8, 9 (waveform B) is increased with the charging circuit of resistor 4 and capacitor 5, and EMOS 8 is conductive at time t1 when it reaches the threshold voltage VTS of EMOS 8. The voltage Vs at point a (waveform C) starts to decrease at time t1 with the difference between the power supply voltage VDD and the threshold voltage VTIG of EMOS 10. At the time t2 when the voltage V1 is greater than the value adding the voltage V9 to the threshold voltage VT9 of EMOS 9, EMOS 9 starts conduction, and the voltage V0 at the output terminal 6 (waveform A) is suddenly decreased. The time Td from the switch 3 turned off to the time t2 is the delay time. By suitably deciding the constants beta8 and beta10determined at the manufacture of EMOS 8 and 10 and satisfying the equation A, the delay time Td is constant independently of the variation in the voltage VDD.

10. 发明专利

JPS58133042A PLL CIRCUIT 失效
公开(公告)号：JPS58133042A
公开(公告)日：1983-08-08
申请号：JP1601582
申请日：1982-02-03
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： YAMATANI MAKOTO , NISHIJIMA OSAMU
IPC分类号： H03L7/10 , H03L7/187
摘要： PURPOSE:To eliminate the need to provide a special circuit countermeasure to an LPF, by detecting digitally a non-locking state and then carrying out an operation to reset the non-locking state to a locking state on the basis of the result of the above-mentioned detection. CONSTITUTION:When a circuit system is not locked, a pulse of H level is produced to only one of two output terminals of a phase comparator 4. This pulse is detected by a D-FF10 or 11 and latched by RS-FF12 and 13 respectively. A control circuit 9 feeds an OR signal 17 of the FF12 and 13 switches multiplexers 15 and 16 to a set state after setting an RS-FF14 in a non-locking mode. In this case, the output of an inverter 22 is set at L level for a fixed period of time, and OR gates 20 and 21 are cut off. Under such conditions, the input of an output circuit 5 is connected to outputs Q and Q' of the FF13. At the same time, the output voltage of an LPF6 changes if the FF14 is set, and the frequency of a voltage control ocillator 7 also changes. Then a normal PLL circuit state is reset after the frequency of the oscillator 7 passes through a desired level.

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