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1. 发明专利

JPH0440791A DIGITAL CONVERGENCE DEVICE 失效
公开(公告)号：JPH0440791A
公开(公告)日：1992-02-12
申请号：JP14898690
申请日：1990-06-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HAMADA MASANORI , MORITA KATSUMI
IPC分类号： H04N9/28
摘要： PURPOSE:To quickly and accurately execute convergence adjustment without needing readjustment by comparing a correcting value to be supplied to a convergence yoke and the correcting value of the output signal of a storing means, detecting that they are coincident and correcting a convergence correcting quantity. CONSTITUTION:A means 12 to select a convergence adjusting point, a means to read the correcting quantity of a 1 frame memory 5 with a clock signal, a correcting means 120 and so on are provided. Then, data except the adjusting point selected by the 1 frame memory 5 with the correcting means 120 are corrected so that the convergence deviation of the peripheral adjusting point generated by the data change of the selected adjusting point may be a same correcting value with comparing the output of a storing means 100 to store the correcting value to be supplied to a convergence yoke 13 of the adjusting points except the selected adjusting point and the correcting value except the selected adjusting point to be supplied to the convergence yoke 13 and with detecting whether they are coincident or not. Thus, readjustment is not needed and convergence adjustment is executed quickly and accurately.

2. 发明专利

JPH0381355B2 失效
公开(公告)号：JPH0381355B2
公开(公告)日：1991-12-27
申请号：JP10988981
申请日：1981-07-13
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HAMADA MASANORI , MORITA KATSUMI
IPC分类号： H04N17/04 , H04N9/28

3. 发明专利

JPH0338797B2 失效
公开(公告)号：JPH0338797B2
公开(公告)日：1991-06-11
申请号：JP7481680
申请日：1980-06-02
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MITSUDA KATSUMI , ADACHI KATSUMI , MORITA KATSUMI , TSUJIHARA SUSUMU
IPC分类号： H04N9/31 , H04N9/28 , H04N17/04

4. 发明专利

JPH02202282A TELEVISION SIGNAL PROCESSOR 失效
公开(公告)号：JPH02202282A
公开(公告)日：1990-08-10
申请号：JP2144889
申请日：1989-01-31
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： SEKI YOSHIO , ISOBE MITSUO , MORITA KATSUMI , NINOMIYA YUICHI , OMURA TOSHIRO
IPC分类号： H04N19/00 , H04N7/01 , H04N11/04 , H04N11/20 , H04N19/132 , H04N19/137 , H04N19/50 , H04N19/80 , H04N19/85
摘要： PURPOSE:To add a freezing function to a TV signal processor in a scale approximately equal to the conventional one by providing two signal switching means, and performing the switching control between a mode to transmit the signal output as a substantial static picture and another mode to transmit the signal output as the output undergone a temporary filter process. CONSTITUTION:A 1st switch circuit 610 selects and outputs a mode control signal input terminal 609 and the input or the output of an HPF 603 based on a mode control signal. A 2nd switch circuit 611 selects the output supplied from a frame memory 604 or the output supplied from a synthesizing circuit 607 based on the mode control signal and supplies it to a signal output terminal 608. For instance, the circuits 610 and 611 select the input of the HPF 603 and the output of the memory 604 respectively with use of the mode control signal. Then a desired screen is frozen and taken out as a static picture in the case the memory 604 is controlled into a read-only mode.

5. 发明专利

JPH02141179A PICTURE SIGNAL PROCESSOR 失效
公开(公告)号：JPH02141179A
公开(公告)日：1990-05-30
申请号：JP29491088
申请日：1988-11-22
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： ISOBE MITSUO , MORITA KATSUMI
IPC分类号： H04N5/265 , H04N5/14 , H04N5/21 , H04N5/45
摘要： PURPOSE:To prevent picture quality deterioration in an input picture signal and to attain 2-screen display by arranging a time axis compression circuit means applying time axis compression to an output of a 1st low pass filter means and a 2nd synthesis circuit means synthesizing the time compression circuit means and a 1st synthesis circuit means. CONSTITUTION:A 1st synthesis circuit 5 synthesizes a low frequency signal component supplied from a 1st LPF 2 via a lead 21 and a switch 61 and an output of a 2nd LPF 4 via a lead 44, the switch 61 is controlled by a mode control signal of a lead 81 so as to block the transmission of a signal from the 1st LPF 2 to the 1st synthesis circuit 5 with a mode control signal of the lead 81. when the 2nd LPF 4 acts like a temporal LPF, the 2nd synthesis circuit 9 sends a moving picture signal suppressing a signal component causing deterioration of picture quality to an output terminal 90. When the 2nd LPF 4 outputs a still picture signal, the signal is synthesized with a picture signal for sub pattern obtained through the reduction of the input picture automatically and the result is sent to the output terminal 90.

6. 发明专利

JPS633513B2 失效
公开(公告)号：JPS633513B2
公开(公告)日：1988-01-25
申请号：JP7169979
申请日：1979-06-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MORITA KATSUMI , MOTOTANI KUNIHIKO , TSUJIHARA SUSUMU , TAKEDA MINORU
IPC分类号： H04N9/28 , H04N17/04

7. 发明专利

JPS6284665A TELEVISION RECEIVER 失效
公开(公告)号：JPS6284665A
公开(公告)日：1987-04-18
申请号：JP22514585
申请日：1985-10-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： MORITA KATSUMI
IPC分类号： H04N5/265 , H04N5/45
摘要： PURPOSE:To perform a master-slave display without any deterioration in picture quality by providing a deflecting circuit which makes a scan on the whole display part with an aspect ratio c:d at a double speed, making a double-speed display at a master picture part, and also displaying a slave picture part without thinning out. CONSTITUTION:An arrival video signal has its synchronizing signals separated by a synchronous separating circuit 11 and is supplied to a scanning signal generating circuit 14 which generates a double-speed horizontal synchronizing signal of frequency which is twice as high as that of the received horizontal synchronizing signal. The output digital video signal of an A/D converter 3 is written on a storage device 4 with the write signal from a control circuit 13. The time-base converted signal from the storage device 4 is processed by an interpolating circuit 15 to obtain a video signal increased in the number of scanning lines. A video signal for a slave image which is written on the storage device 23 for one vertical period in synchronization with a slave image video signal is read out in synchronization with a master image, sent to a D/A converter 6 for a slave image display period with the signal from the control circuit 15 through a switching circuit 5, and amplified by an output circuit 8 to a desired amplitude; and then a cathode-ray tube 10 is driven to obtain the slave image.

8. 发明专利

JPS6269723A SAMPLING CLOCK PHASE CONTROLLER FOR ANALOG/DIGITAL CONVERTER 失效
公开(公告)号：JPS6269723A
公开(公告)日：1987-03-31
申请号：JP20927285
申请日：1985-09-20
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： NAKAYAMA TADANORI , MORITA KATSUMI , NINOMIYA YUICHI , OTSUKA YOSHIMICHI , IZUMI YOSHINORI , GOSHI SEIICHI
IPC分类号： H03M1/12 , H03L7/08 , H04N5/06 , H04N5/14 , H04N7/00 , H04N7/015
摘要： PURPOSE:To immediately obtain a picture with less ringing without adjustment even if any signals are inputted by automatically setting the sampling phase of an A/D converter to a phase, where ringing is minimum, in accordance with an input signal. CONSTITUTION:A VTR signal and a demodulated satellite broadcast signal are inputted to the fixed terminal of a changeover switch 14. On the other hand, an addition data A21 has a value adjusting the sampling phase of the A/D converter 17 so that the ringing of a picture when the satellite broadcast signal is received can be minimized, while an addition data B22 has a value adjusting the sampling phase of the converter 17 so that the ringing of a picture be minimized when the VTR signal is received. Interlocking with the switch 14, the changeover switch 20 is switched. When the input signal is the satellite broadcast signal, the data A21 is selected. The data B22 is selected when the VTR signal is given. Thus even any signals are inputted, the picture with less ringing can be obtained immediately.

9. 发明专利

JPS6184977A Television receiving set 失效
标题翻译：电视接收机
公开(公告)号：JPS6184977A
公开(公告)日：1986-04-30
申请号：JP20740184
申请日：1984-10-03
申请人： Matsushita Electric Ind Co Ltd
发明人： MORITA KATSUMI , HAMADA MASANORI
IPC分类号： H04N5/45
摘要： PURPOSE: To display a master picture and a slave picture separately on the same picture and to minimize the missing part of the master picture by providing a storing device different in speed of writing and reading for displaying master picture signals without causing distortion and a storing device different in speed of writing and reading for the slave picture.
CONSTITUTION: Video signals for a master picture from an input terminal are processed in a video signal processing circuit 2, and luminance signals and color difference signals are A/D converted 3 and stored in a storing device 4. Synchronizing signals separated by a synchronizing separator circuit 11 are applied to a deflecting yoke 9 through a deflecting circuit 12. CRT10 is raster scanned and applied to a controlling circuit 13. Video signals for a slave picture from an input terminal 20 are processed in a video signal processing circuit 21 and stored in a storing device 23, and a synchronizing signal separated by a synchronizing separator circuit 24 is applied to the circuit 13. Writing and reading of devices 4, 23 are controlled respectively by the control of the circuit 13. At the same time, a switching circuit 5 is controlled to display the master picture from the right side and the slave picture at the lower left, and the missing part of the master picture is minimized.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过提供不同于写入和读取速度的存储装置来显示主图像信号而不引起失真并且存储设备，在同一图像上分别显示主图像和从属图像并最小化主图像的缺失部分写入和读取速度不同于从属画面。构成：在视频信号处理电路2中处理来自输入端的主画面的视频信号，并对亮度信号和色差信号进行A / D转换3并存储在存储装置4中。同步信号由同步分离器电路11通过偏转电路12施加到偏转磁轭9. CRT10被光栅扫描并施加到控制电路13.来自输入端子20的从画面的视频信号在视频信号处理电路21中被处理并存储在存储装置23和由同步分离器电路24分离的同步信号被施加到电路13.装置4,23的写入和读取分别由电路13的控制来控制。同时，开关电路 5被控制以从右侧显示主图像，并在左下方显示从属图像，并且将主图像的缺失部分最小化。

10. 发明专利

JPS5989088A TELEVISION TRANSMITTER OF HIGH IMAGE RESOLUTION 失效
公开(公告)号：JPS5989088A
公开(公告)日：1984-05-23
申请号：JP19917282
申请日：1982-11-12
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： KOGA TOYOKATSU , TAKEDA MINORU , FUJISAWA SEIJI , MORITA KATSUMI , TAIRA HIDEKAZU
IPC分类号： H04N9/66 , H04N11/14 , H04N11/24
摘要： PURPOSE:To transmit a TV signal of high image resolution by extracting an image pickup signal of a wide band out of a balanced modulating circuit and giving the color signal processing to the image pickup signal so as to secure the compatibility with the NTSC standard system. CONSTITUTION:A balanced modulating circuit 24 produces a luminance signal of a wide band and color difference signals, e.g., R-Y and B-Y from image pickup signals of three primary colors R, G and B. The circuit 24 limits the signal Y and two color difference signals to an m-fold band compared with the NTSC standard system. Then the rectangular double phase amplitude modulation is given to those color difference signals with an (m+1)-fold subcarrier frequency compared with the chrominance subcarrier frequency of standard system. This output signal is sent to a mixer 28 via a BPF25 and mixed with a subcarrier frequency (m+2) times as much as the frequency of chrominance subcarrier to be converted into a chrominance signal of a difference chorminance subcarrier frequency. This chrominance signal is multiplexed with the signal Y, and at the same time a burst signal, a syncrhonizing signal and a pilot signal of (m) times as much as a wobbling signal are added 23 together. Thus a TV signal of high image resolution is delivered.

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