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1. 发明专利

JPH02202282A TELEVISION SIGNAL PROCESSOR 失效
公开(公告)号：JPH02202282A
公开(公告)日：1990-08-10
申请号：JP2144889
申请日：1989-01-31
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： SEKI YOSHIO , ISOBE MITSUO , MORITA KATSUMI , NINOMIYA YUICHI , OMURA TOSHIRO
IPC分类号： H04N19/00 , H04N7/01 , H04N11/04 , H04N11/20 , H04N19/132 , H04N19/137 , H04N19/50 , H04N19/80 , H04N19/85
摘要： PURPOSE:To add a freezing function to a TV signal processor in a scale approximately equal to the conventional one by providing two signal switching means, and performing the switching control between a mode to transmit the signal output as a substantial static picture and another mode to transmit the signal output as the output undergone a temporary filter process. CONSTITUTION:A 1st switch circuit 610 selects and outputs a mode control signal input terminal 609 and the input or the output of an HPF 603 based on a mode control signal. A 2nd switch circuit 611 selects the output supplied from a frame memory 604 or the output supplied from a synthesizing circuit 607 based on the mode control signal and supplies it to a signal output terminal 608. For instance, the circuits 610 and 611 select the input of the HPF 603 and the output of the memory 604 respectively with use of the mode control signal. Then a desired screen is frozen and taken out as a static picture in the case the memory 604 is controlled into a read-only mode.

2. 发明专利

JPS6269723A SAMPLING CLOCK PHASE CONTROLLER FOR ANALOG/DIGITAL CONVERTER 失效
公开(公告)号：JPS6269723A
公开(公告)日：1987-03-31
申请号：JP20927285
申请日：1985-09-20
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： NAKAYAMA TADANORI , MORITA KATSUMI , NINOMIYA YUICHI , OTSUKA YOSHIMICHI , IZUMI YOSHINORI , GOSHI SEIICHI
IPC分类号： H03M1/12 , H03L7/08 , H04N5/06 , H04N5/14 , H04N7/00 , H04N7/015
摘要： PURPOSE:To immediately obtain a picture with less ringing without adjustment even if any signals are inputted by automatically setting the sampling phase of an A/D converter to a phase, where ringing is minimum, in accordance with an input signal. CONSTITUTION:A VTR signal and a demodulated satellite broadcast signal are inputted to the fixed terminal of a changeover switch 14. On the other hand, an addition data A21 has a value adjusting the sampling phase of the A/D converter 17 so that the ringing of a picture when the satellite broadcast signal is received can be minimized, while an addition data B22 has a value adjusting the sampling phase of the converter 17 so that the ringing of a picture be minimized when the VTR signal is received. Interlocking with the switch 14, the changeover switch 20 is switched. When the input signal is the satellite broadcast signal, the data A21 is selected. The data B22 is selected when the VTR signal is given. Thus even any signals are inputted, the picture with less ringing can be obtained immediately.

3. 发明专利

JPH02141184A PICTURE SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH02141184A
公开(公告)日：1990-05-30
申请号：JP29492788
申请日：1988-11-22
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： ISOBE MITSUO , HAMADA MASANORI , MORITA KATSUMI , NINOMIYA YUICHI
IPC分类号： H04N19/102 , H04N5/14 , H04N5/46 , H04N7/015 , H04N7/24 , H04N11/00 , H04N11/24 , H04N19/00 , H04N19/132 , H04N19/137 , H04N19/196 , H04N19/42 , H04N19/423 , H04N19/59 , H04N19/80
摘要： PURPOSE:To make high quality signal processing function and low cost compatible by providing a mode control means to apply control for prescribed signal processing and processing a MUSE signal and an NTSC signal with a substantially common signal processing circuit. CONSTITUTION:In the case of selecting an NTSC signal at a signal input terminal 11 with a switch 21, frame delay processing is applied to all picture signal components and the NTSC signal of one preceding and 2-preceding frames with respect to the input signal is sent to leads 52, 61. Then the signal is subject to desired signal processing and a 1-frame movement detection signal based on one-frame difference signal is sent to a lead 603. When a control signal processing the MUSE signal is supplied, a 1st - a 3rd frame memory apply one frame delay processing to the MUSE signal and the MUSE signal of one and 2 preceding frames is sent to the leads 52, 61. Thus, the NTSC signal and the MUSE signal are subject to cryptographic processing by the same circuit substantially.

4. 发明专利

JPH02141181A TELEVISION RECEIVER 失效
公开(公告)号：JPH02141181A
公开(公告)日：1990-05-30
申请号：JP29492688
申请日：1988-11-22
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： MORITA KATSUMI , ISOBE MITSUO , NINOMIYA YUICHI , GOSHI SEIICHI
IPC分类号： H04N7/12 , H04N7/00 , H04N7/015 , H04N19/00 , H04N19/132 , H04N19/137 , H04N19/423 , H04N19/59 , H04N19/80 , H04N19/85
摘要： PURPOSE:To obtain a freeze picture without any multi-line fog with excellent picture quality by providing a frame memory constituted in the unit of fields and using two consecutive field signals for a still picture part and a single field signal for a moving picture part. CONSTITUTION:A frame memory 17 consists of two field memories 30, 31, the existing field is stored in the field memory 30 and the preceding field is stored in the field memory 31. Other moving control signal from a moving detection circuit 13 is stored for one frame in field memories 20, 21. For example, the existing field in an odd field is used to display the entire picture independently of the still picture and the moving picture. The still picture displays the preceding field and the moving picture displays the existing field A' in an even number field and the field A' is displayed in place of the field A. Thus, the existing field is displayed on the still region of the preceding field subject to missing to obtain a picture almost without multi-line fog.

5. 发明专利

JPH02141183A TELEVISION RECEIVER 失效
公开(公告)号：JPH02141183A
公开(公告)日：1990-05-30
申请号：JP29492588
申请日：1988-11-22
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： MORITA KATSUMI , ISOBE MITSUO , NINOMIYA YUICHI , GOSHI SEIICHI
IPC分类号： H04N7/12 , H04N7/015 , H04N7/24 , H04N19/00 , H04N19/117 , H04N19/132 , H04N19/137 , H04N19/162 , H04N19/423 , H04N19/59 , H04N19/80 , H04N19/85
摘要： PURPOSE:To obtain a frozen video signal by providing two signal changeover switches and using a frame memory being a component of a temporal low pass filter as a freezing frame memory. CONSTITUTION:When a freeze signal comes to a freeze signal input terminal, switches 1, 20 and 2, 21 are thrown to the position as shown in figure. An output signal of a mixing circuit 14 is stored in a frame memory 17 via the switch 1, 20. The video signal stored in the frame memory 17 is read repetitively and sent to an output terminal 18 via the switch 2, 21. Thus, a video signal decoded into a high definition television signal and frozen is obtained at the output terminal 18. Thus, it is not required to provide a freeze frame memory newly by having only to add two switches and freeze display is attained without increasing the circuit scale.

6. 发明专利

JPS63164780A TELEVISION SIGNAL RECEIVER 失效
公开(公告)号：JPS63164780A
公开(公告)日：1988-07-08
申请号：JP31229686
申请日：1986-12-26
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： ISOBE MITSUO , MORITA KATSUMI , NINOMIYA YUICHI , OTSUKA YOSHIMICHI , IZUMI YOSHINORI
IPC分类号： H04N7/01
摘要： PURPOSE:To eliminate the deterioration in the picture quality attended with scanning conversion by using an output signal of a moving detection circuit as a control signal, using signals of two adjacent fields for a still picture part and using only a signal of a single field for the moving picture part so as to obtain the signal of the sequential scanning system. CONSTITUTION:A 1st inter-field interpolation processing circuit 71 uses an output of a 4th signal processing circuit 40 as a sampling signal and uses an output of a delay circuit 60 as an interpolation signal to apply the inter-field interpolation processing as to the still picture part. A 2nd inter-field interpolation processing circuit 72 uses an output of the delay circuit 60 as a sampling signal and uses an output of the 4th signal processing circuit 40 as an interpolation signal to apply the inter-field interpolation processing as to the still picture part. A 5th signal processing circuit 82 uses one of outputs of the 1st and 2nd inter-field interpolation processing circuits 71, 72 whose output signals have a different time by one field relatively as the sampling scanning line signal and uses the other as the interpolation scanning line signal to send a 1st sequential scanning signal. A 6th signal processing circuit 85 sends a 2nd sequential scanning signal from the output of the 1st inter-field interpolation processing circuit 71 only. Thus, the deterioration of picture quality is prevented.

7. 发明专利

JPS55163987A DIGITAL CONVERGENCE UNIT 失效
公开(公告)号：JPS55163987A
公开(公告)日：1980-12-20
申请号：JP7207979
申请日：1979-06-07
申请人： JAPAN BROADCASTING CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： KAWAMOTO TAROU , KUBO TOKUJI , TSUJIHARA SUSUMU , MORITA KATSUMI , MOTOTANI KUNIHIKO , MITSUDA KATSUMI , TAKEDA MINORU
IPC分类号： H04N9/28 , H04N17/04
摘要： PURPOSE:To save memory capacity while shortening the time of adjustments by previously storing data for adjustments on crosses on a screen and further by providing a fine adjusting function. CONSTITUTION:One-frame memory 31 consists of ROM for four high-order bits, for example, and nonvolatile RAM for four low-order bits. In this ROM, four bits of the needed correction value regarding each cross-shaped adjustment point on a screen are previously written. This data is repeatedly read out. In RAM, correction data concerning all adjustment points are written for fine adjustments by data reversible counter 34. Next, the contents of memory 31 are read out and after interpolated, D/A-converted 9 to output convergence signals via LPF10. Thus, while the adjustment time can be shortened, the contents of ROM are repeatedly read out to generate a correction value of another adjustment point, so that the capacity of ROM can be saved.

8. 发明专利

JPH0350965A TELEVISION SIGNAL PROCESSING UNIT 失效
公开(公告)号：JPH0350965A
公开(公告)日：1991-03-05
申请号：JP18649589
申请日：1989-07-19
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： ISOBE MITSUO , MORITA KATSUMI , NINOMIYA YUICHI
IPC分类号： H04N5/21 , H04B1/10 , H04N5/44 , H04N11/08 , H04N11/24
摘要： PURPOSE:To simplify a receiver and to reduce the cost by providing an input processing circuit, a noise elimination arithmetic circuit and a frame delay circuit or the like, applying noise elimination processing using correlation between frames and applying prescribed detection processing. CONSTITUTION:A received TV signal fed to a signal input terminal 1 is inputted to an input processing circuit 6 via a clamp circuit 3 and an A/D converter 4 and decoding processing for transmission gamma processing or the like for nonlinear pre-emphasis processing and pseudo constant brightness transmission is applied. Then a video signal component subject to multiplex sampling from the circuit 6 and a time division multiplex signal from at least frame synchronizing signal and clamp level signal are fed to a noise reduction arithmetic circuit (NR circuit) 7 for reducing or eliminating the noise component. Then the noise elimination processing employing the circuit 7 and the correlation between frames via frame delay circuits 8, 9 is implemented and prescribed detection processing is applied. Thus, the scale of the unit is simplified and highly stable operation is attained.

9. 发明专利

JPS55163988A DIGITAL CONVERGENCE UNIT 失效
公开(公告)号：JPS55163988A
公开(公告)日：1980-12-20
申请号：JP7208079
申请日：1979-06-07
申请人： JAPAN BROADCASTING CORP , MATSUSHITA ELECTRIC IND CO LTD
发明人： KAWAMOTO TAROU , KUBO TOKUJI , MOTOTANI KUNIHIKO , MORITA KATSUMI , MITSUDA KATSUMI , TSUJIHARA SUSUMU , TAKEDA MINORU
IPC分类号： H04N9/28
摘要： PURPOSE:To lessen a color shift at the circumference of a screen by storing a convergence correction value, obtained by extrapolation, of the outside of an adjustment point. CONSTITUTION:The convergence correction value of each adjustment point is written in one-frame memory 37 via data reversible counter 2. Next, the contents of memory 37 are sequentially read out and processed by subtracting circuit 32 and adding circuit 33 to find the correction value of the further outside of an adjustment point by extrapolation. Then, the extrapolation value obtained as mentioned above is written at a fixed address in memory 37. Then, the contents of memory 37 are read out and interpolated to generate the correction value of each scanning line, which is D/A-converted 9 to output convergence signal via LPF10. Thus, corrections of high precision can be made on the entire screen by lessening a shift in convergence at the circumference of the screen.

10. 发明专利

JPH0350988A SYSTEM CONVERTER 失效
公开(公告)号：JPH0350988A
公开(公告)日：1991-03-05
申请号：JP18649889
申请日：1989-07-19
申请人： MATSUSHITA ELECTRIC IND CO LTD , JAPAN BROADCASTING CORP
发明人： MORITA KATSUMI , ISOBE MITSUO , KOGA TOYOKATSU , HAMADA MASANORI , NINOMIYA YUICHI , IZUMI YOSHINORI
IPC分类号： H04N3/22 , G09G1/16 , H04N11/08 , H04N11/20 , H04N11/22 , H04N11/24
摘要： PURPOSE:To display a signal onto a receiver of the current 525-line system with an aspect ratio of 16:9 by providing a circuit thinning 3 scanning lines of a MUSE signal into one and a circuit converting the time axis of the MUSE signal into the 525-line system. CONSTITUTION:A video signal of a MUSE signal comes to an input terminal 1 and a pre-filter 2 eliminates the distortion caused by thinning the scanning line number into 1/3. Then the time axis of 375-line of luminance signal interleaved into 1/3 by an extraction circuit 4 is converted into the scanning of 525-line system from the MUSE scanning at a luminance scanning line conversion circuit. On the other hand, a color decode circuit 3 decodes two synchronous color signals, the extraction circuit 5 extracts one from 3 lines and a color scanning conversion circuit 7 applies time axis conversion from the MUSE scanning into the scanning of 525-line system. The luminance signal converted into the 525 line system and two color signals are given via a D/A converter 8, and a luminance signal whose aspect ratio is 16:9 is obtained at an output terminal 9 and the color signals whose aspect ratio is 16:9 are obtained at output terminals 10, 11.

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