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1. 发明专利

JPH0462150B2 失效
公开(公告)号：JPH0462150B2
公开(公告)日：1992-10-05
申请号：JP17341383
申请日：1983-09-19
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , TANAKA SHINICHI , ISHIBASHI HIROMICHI
IPC分类号： G11B7/00 , G11B7/005 , G11B7/085 , G11B19/02 , G11B20/10 , G11B21/08

2. 发明专利

JPH0132592B2 失效
公开(公告)号：JPH0132592B2
公开(公告)日：1989-07-06
申请号：JP15652281
申请日：1981-09-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , EGUCHI TAKASHI
IPC分类号： G11B20/10 , G11B20/18

3. 发明专利

JPS6353737B2 失效
公开(公告)号：JPS6353737B2
公开(公告)日：1988-10-25
申请号：JP16506779
申请日：1979-12-18
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , ODAGI KANJI
IPC分类号： H03M1/66 , H03H17/00 , H03H17/02 , H03M1/00 , H03M1/08

4. 发明专利

JPS6219092B2 失效
公开(公告)号：JPS6219092B2
公开(公告)日：1987-04-27
申请号：JP2949576
申请日：1976-03-17
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： SANO SHINYA , GOTO HIROSHI , HIROTA YUTAKA
IPC分类号： H03F1/26 , H03F1/34 , H03H11/28 , H03H11/46 , H04R3/00

5. 发明专利

JPS6033740A ERROR DETECTING AND CORRECTING DEVICE 失效
公开(公告)号：JPS6033740A
公开(公告)日：1985-02-21
申请号：JP14302183
申请日：1983-08-03
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： AKIYAMA TOSHIHIDE , SENOO TAKANORI , HIROTA YUTAKA , TANAKA SHINICHI
IPC分类号： H03M13/00 , G11B20/18 , H03M13/29
摘要： PURPOSE:To improve the error correcting accuracy by providing a means for discriminating whether or not a final decoded output is interpolated through the combination of a decoded state of each decoder in decoding an information code coded by plural error detecting and correcting device. CONSTITUTION:After an input code is decoded by the 1st decoder 3 at first, the code is fed to the 2nd decoder 4 and decoded. The decoded state signal of the 1st decoder 3 and the 2nd decoder 4 is fed to an interpolation condition discriminating circuit 5. The circuit 5 applies logical operation based on both the decoded state signals and detects a missing/error correction of the 2nd decoder 4 and it is informed to an interpolation circuit 6. The interpolation circuit 6 receives it, applies interpolation and correction of a decoded signal fed from the 2nd decoder 4 and leads the result to a succeeding circuit as correct final information.

6. 发明专利

JPS5837827A PCM SOUND RECORDER AND REPRODUCER 失效
公开(公告)号：JPS5837827A
公开(公告)日：1983-03-05
申请号：JP13688081
申请日：1981-08-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , ODAGI KANJI
IPC分类号： G11B20/16 , G11B20/10 , H04L7/06
摘要： PURPOSE:To simplify the constitution of circuit for a PCM sound recorder/ reproducer, by superposing a master clock on a PCM signal which is based on a reference TV signal with division of frequency to transmit them when the PCM signal is recorded and reproduced by means of a VTR, etc. CONSTITUTION:A PCM signal is fed to a terminal 1, and a master clock is fed to a terminal 2. In a resonance circuit 4, a coil L1 and a capacitor C1 resonate with the frequency of the clock. The signals of the terminals 1 and 2 are mixed 5 via a buffer circuit 3 and the circuit 4, respectively and applied to a buffer circuit 6. The master clock is superposed on the PCM signal with division of frequency and fed to a terminal 7. 'The output of the terminal 7 is applied to a terminal 8, and an L2 and a C2 resonate with the frequency of the master clock to form an LPF that transmits only the PCM signal. Then a C3 and the base impedance of a transistor TR form an HPF. Each output is fed to a voltage comparator 14, and only the master clock can be extracted to a terminal 12.

7. 发明专利

JPS5837823A AMPLITUDE DETECTING CIRCUIT FOR HORIZONTAL SYNCHRONIZING SIGNAL OF PCM SOUND RECORDER AND REPRODUCER 失效
公开(公告)号：JPS5837823A
公开(公告)日：1983-03-05
申请号：JP6001082
申请日：1982-04-09
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , EGUCHI TAKASHI
IPC分类号： G11B20/10 , G11B20/24
摘要： PURPOSE:To eliminate completely moises caused by the disturbance of the horizontal synchronizing signal of a reproduction processing system, by producing different logical outputs in accordance with the detection of coincidence between the width of the horizontal synchronizing signal in a reproduced PCM signal and the width of the signal format. CONSTITUTION:The synchronizing signal E, horizontal synchronizing signal T and clock signal H in a PCN signal which is based on a reference TV signal and reproduced actually are inputted. Then whether or not the logical level of the signal T which is acutually reproduced is ''0'' is detected for a period corresponding to that covering from the falling time of the horizontal synchronizing signal of the reproduced PCM signal to the amplitude of the horizontal synchronizing signal of the PCM signal format. The prescribed logical output O is produced when all logical levels are ''0'' in the period corresponding to the width of the signal T.

8. 发明专利

JPS5837820A CONTINUOUS MUTING COUNTER OF PCM SOUND RECORDER AND REPRODUCER 失效
公开(公告)号：JPS5837820A
公开(公告)日：1983-03-05
申请号：JP5887982
申请日：1982-04-07
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , EGUCHI TAKASHI
IPC分类号： G11B20/18 , G11B20/22
摘要： PURPOSE:To prevent the continious switching of a reproducing system, by producing the muting signal only in the first horizontal period when there is a variance larger than a prescribed number of bits between the data signal and the horizontal synchronizing signal in a PCM signal. CONSTITUTION:A prescribed logical input J is applied to a gate 4-3 when there is a variance larger than a prescribed number of bits between the data signal and the horizontal synchronizing signal in a PCM signal which is based on a standard TV signal. A circuit 3 delays th input J by a prescribed horizontal period. The gate 4-3 is opened and closed with a delay output K to deliver the input J as a muting signal G through the gate 4-3 only in the first horizontal period. Then the input J is cut off in the subsequent prescribed horizontal period.

9. 发明专利

JPS5837818A PCM SOUND RECORDER AND REPRODUCER 失效
公开(公告)号：JPS5837818A
公开(公告)日：1983-03-05
申请号：JP13688181
申请日：1981-08-31
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , HAGIWARA SHIGERU
IPC分类号： G11B20/10 , G11B20/14
摘要： PURPOSE:To prevent a malfunction when a signal is processed, by replacing the synchronizing signal part in a PCM signal which is produced from a tape with the synchronizing signal which is previously produced. CONSTITUTION:When a head switching signal is detected 9 and 10, a counter 11 counts the time during which a vertical synchronizing signal emerges. The result of this count is stored in the latches 13-16. The count value of N times which is obtained before the storage of the latches 13-16 is compared 18 with the count value of this time. A coincidence output D is fed to control circuits 21 and 24. While a PCM signal reproduced from a tape is fed to a synchronizing signal replacing circuit 23 and a vertical synchronizing signal detector circuit 19. The vertical synchronizing signal E is fed to control circuit 21 in the form of a delaying signal G and simultaneously with the output D. As a result, a vertical synchronizing signal generator 22 feeds the synchronizing signal F equivalent to the signal E, an equalized pulse signal, etc. to the circuit 23. Then the circuit 24 delivers the reproduced synchronizing signal after replacing it with the signal F.

10. 发明专利

JPS5837806A DETECTING CIRCUIT OF DATA SYNCHRONIZING SIGNAL FOR PCM SOUND RECORDER AND REPRODUCER 失效
公开(公告)号：JPS5837806A
公开(公告)日：1983-03-05
申请号：JP15652181
申请日：1981-09-30
申请人： MATSUSHITA ELECTRIC IND CO LTD
发明人： HIROTA YUTAKA , EGUCHI TAKASHI
IPC分类号： G11B20/10 , G11B20/14 , H04L7/08
摘要： PURPOSE:To ensure the accurate detection of the bit and data, by supplying both data and clock signals contained in a PCM signal which is based on the standard TV signal and delivering 1 and 0 in the case of the synchronizing signal of 1010 in the data signal and in other cases respectively. CONSTITUTION:The data signal, the synchronizing signal and the master locking signal are applied to terminals A-C respectively. A clock signal generating circuit 17 generates the clocking signal H for punching the PCM signal. The signal H and the outputs of a data signal generating circuit 18 and a synchronizing signal generating circuit 19 are supplied to a data signal delaying circuit 1 and a synchronizing signal delaying circuit 2 to be delayed there. While the output of the circuit 18 is supplied to a data signal switching circuit 5, and the data synchronizing signal ''1010'' contained in the output signal Q of the circuit 5 is detected through a data synchronizing signal detecting circuit 6. Thus, 1 is delivered from the circuit 6. Otherwise the circuit 6 delivers O. A bit deciding circuit 7 supplies the outputs of the circuit 6 and a horizontal synchonrizing signal detecting circuit 13 as well as the signal H and can decides the number of normal bits existing between the horizontal sycnhronizing signal and the data synchronizing signal.

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