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    • 10. 发明专利
    • Transmission method, transmission circuit, and transmission system
    • 传输方式,传输电路和传输系统
    • JP2009206958A
    • 2009-09-10
    • JP2008048313
    • 2008-02-28
    • Elpida Memory IncNec Corpエルピーダメモリ株式会社日本電気株式会社
    • SAITO HIDEAKIIKEDA HIROAKI
    • H04L25/49H04L25/493
    • H04L25/4906
    • PROBLEM TO BE SOLVED: To reduce a number of charging and discharging of wiring between chips per one clock cycle to reduce a consumption power without using multi power sources, such as a multi potential transmission, and without using a high speed clock or a high speed delay control required for the pulse width modulation data transmission system.
      SOLUTION: In a transmission side chip 30, a counter 34 outputs a count value obtained by up-counting the eight-multiplied clock CK8 of a clock CLK to a digital comparator 35. The digital comparator 35 outputs a high level signal when the counter value is equal to or more than a value of 3-bit transmitted data from flipflops 31 to 33. A selector 37 outputs a wave-like signal which performs amplitude transition once in rising or falling during one clock cycle. An output buffer 38 outputs the signal output from the selector 37 to an exterior penetrating wiring 50 of the transmission side chip 30.
      COPYRIGHT: (C)2009,JPO&INPIT
    • 要解决的问题:为了减少每个时钟周期的芯片之间的布线的充电和放电的数量,以降低功耗而不使用多电源,例如多电位传输,并且不使用高速时钟或 脉宽调制数据传输系统所需的高速延迟控制。 解决方案:在发送侧芯片30中,计数器34将通过将时钟CLK的八倍时钟CK8向上计数而获得的计数值输出到数字比较器35。数字比较器35输出高电平信号 计数器值等于或大于来自触发器31至33的3位发送数据的值。选择器37输出在一个时钟周期期间在上升或下降中执行幅度转换一次的波形信号。 输出缓冲器38将从选择器37输出的信号输出到发送侧芯片30的外部穿透布线50.版权所有(C)2009,JPO&INPIT