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1. 发明专利

JP2013030593A Semiconductor devices, semiconductor module structure formed by vertically laminated semiconductor devices, and manufacturing method of semiconductor module structure 审中-公开
标题翻译：半导体器件，通过垂直层叠半导体器件形成的半导体器件结构以及半导体器件结构的制造方法
公开(公告)号：JP2013030593A
公开(公告)日：2013-02-07
申请号：JP2011165200
申请日：2011-07-28
申请人： J Devices:Kk , 株式会社ジェイデバイス
发明人： YAMAGATA OSATAKE , KATSUMATA AKIO , INOUE KOJI , SAWACHI SHIGENORI , ITAKURA SATORU , YAMAJI YASUHIRO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/97 , H01L24/19 , H01L24/24 , H01L24/29 , H01L24/32 , H01L24/82 , H01L25/105 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/12105 , H01L2224/24226 , H01L2224/2518 , H01L2224/29099 , H01L2224/2919 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2225/1035 , H01L2225/1058 , H01L2225/1094 , H01L2924/01029 , H01L2924/014 , H01L2924/078 , H01L2924/0951 , H01L2924/12041 , H01L2924/12042 , H01L2924/15311 , H01L2924/15321 , H01L2924/1579 , H01L2924/15798 , H01L2924/00014 , H01L2224/82 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which forms a vertical lamination structure and enables LSI chips, having different sizes, to be easily and vertically laminated.SOLUTION: A semiconductor device includes: an organic substrate 1; a through via 4 penetrating through the organic substrate 1 in the thickness direction; an external electrode 5b and an internal electrode 5a provided on both surfaces of the organic substrate 1 and electrically connecting with the through via 4; a semiconductor element 2 mounted on one main surface of the organic substrate 1 through an adhesive layer 3 with an element circuit surface facing up; an insulation material layer 6 sealing the semiconductor element 2 and an area surrounding the semiconductor element 2; a metal thin film wiring layer 7 provided in the insulation material layer 6 and partially exposing on an external surface; a metal via 10 electrically connecting with the metal thin film wiring layer 7; and an external electrode 9 formed on the metal thin film wiring layer 7. The metal thin film wiring layer 7 electrically connects an electrode disposed on the element circuit surface of the semiconductor element 2, the internal electrode 5a, the metal via 10, and the external electrode 9 formed on the metal thin film wiring layer 7.
摘要翻译：要解决的问题：提供一种形成垂直层压结构的半导体器件，并且能够容易且垂直地层叠具有不同尺寸的LSI芯片。解决方案：半导体器件包括：有机衬底1; 穿过有机基板1的厚度方向的贯通孔4; 设置在有机基板1的两面并与通孔4电连接的外部电极5b和内部电极5a; 半导体元件2，其通过具有面向上的元件电路表面的粘合剂层3安装在有机基板1的一个主表面上; 密封半导体元件2的绝缘材料层6和围绕半导体元件2的区域; 设置在绝缘材料层6中并部分地暴露在外表面上的金属薄膜布线层7; 与金属薄膜布线层7电连接的金属通孔10; 以及形成在金属薄膜布线层7上的外部电极9.金属薄膜布线层7电连接设置在半导体元件2的元件电路表面上的电极，内部电极5a，金属通孔10和形成在金属薄膜布线层7上的外部电极9.版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2014093430A Semiconductor device, semiconductor laminated module structure, laminated module structure and manufacturing methods of those 有权
标题翻译：半导体器件，半导体层压模块结构，层压模块结构及其制造方法
公开(公告)号：JP2014093430A
公开(公告)日：2014-05-19
申请号：JP2012243276
申请日：2012-11-05
申请人： J Devices:Kk , 株式会社ジェイデバイス
发明人： INOUE KOJI , KATSUMATA AKIO , SAWACHI SHIGENORI , YAMAGATA OSATAKE
IPC分类号： H01L23/12 , H01L21/56 , H01L23/29 , H01L23/31 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L24/96 , H01L24/97 , H01L2224/12105 , H01L2224/19 , H01L2224/32225 , H01L2224/73267 , H01L2224/92244 , H01L2224/97 , H01L2224/82 , H01L2224/83 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which easily enables vertical lamination of LSI chips having different sizes from each other.SOLUTION: A semiconductor device comprises: an insulating substrate; a semiconductor element mounted on one principal surface of the insulating substrate with an element circuit surface up; a first insulating material layer A for encapsulating a top face of the element circuit surface of the semiconductor element and a top face of the insulating substrate around the element circuit surface; a first metal thin film wiring layer which is arranged on the first insulating material layer A and a part of which is exposed outside; a first insulating material layer B arranged on the first metal thin film wiring layer; a second insulating material layer arranged on the other principal surface of the insulating substrate; a second metal thin film wiring layer which is arranged in the second insulating material layer and a part of which is exposed outside; a via which pierces the insulating substrate and electrically connects the first metal thin film wiring layer and the second metal thin film wiring layer; and an external electrode formed on the first metal thin film wiring layer. The semiconductor device has a structure in which the second metal thin film wiring layer, an electrode arranged on the element circuit surface of the semiconductor element, the first metal thin film wiring layer, the via and the external electrode on the first metal thin film wiring layer are electrically connected.
摘要翻译：要解决的问题：提供一种容易实现彼此不同尺寸的LSI芯片的垂直层叠的半导体器件。解决方案：半导体器件包括：绝缘基板; 半导体元件安装在绝缘基板的一个主表面上，元件电路表面向上; 用于封装半导体元件的元件电路表面的顶面和围绕元件电路表面的绝缘基板的顶面的第一绝缘材料层A; 第一金属薄膜布线层，其布置在第一绝缘材料层A上并且其一部分暴露在外部; 布置在第一金属薄膜布线层上的第一绝缘材料层B; 布置在所述绝缘基板的另一个主表面上的第二绝缘材料层; 第二金属薄膜布线层，其布置在第二绝缘材料层中并且其一部分暴露在外部; 穿过所述绝缘基板并将所述第一金属薄膜布线层与所述第二金属薄膜布线层电连接的通孔; 以及形成在第一金属薄膜布线层上的外部电极。半导体器件具有这样的结构，其中第一金属薄膜布线层，布置在半导体元件的元件电路表面上的电极，第一金属薄膜布线层，通孔和外部电极在第一金属薄膜布线层电连接。

3. 发明专利

JP2012119574A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012119574A
公开(公告)日：2012-06-21
申请号：JP2010269499
申请日：2010-12-02
申请人： J Devices:Kk , 株式会社ジェイデバイス
发明人： SAWACHI SHIGENORI
IPC分类号： H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2224/16
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device having metal post parts which are manufactured at low cost by using a simple method and deal with the increased number of electrodes and the reduction of semiconductor package size, and to provide a manufacturing method of the semiconductor device.SOLUTION: A semiconductor device includes: a first substrate in which multiple first electrode parts are formed around a semiconductor chip mounting area; a semiconductor chip having multiple electrodes and mounted on the semiconductor chip mounting area of a substrate; a second substrate in which multiple second electrode parts are formed on a surface facing the first substrate and a wiring layer is formed; and multiple metal post parts which electrically connect the multiple second electrode parts with the multiple first electrode parts and have shapes, each of which tapers from a portion contacting with the second electrode part toward a portion contacting with the first electrode part.
摘要翻译：要解决的问题：提供一种半导体器件，其具有通过使用简单的方法以低成本制造的金属柱部件并且处理增加的电极数量和减小半导体封装尺寸，并提供制造方法的半导体器件。解决方案：半导体器件包括：第一衬底，其中围绕半导体芯片安装区域形成多个第一电极部分; 具有多个电极且安装在基板的半导体芯片安装区域上的半导体芯片; 第二基板，其中在面向所述第一基板的表面上形成多个第二电极部分，并且形成布线层; 以及将多个第二电极部分与多个第一电极部分电连接并具有形状的多个金属支柱部件，其各自从与第二电极部件接触的部分向与第一电极部件接触的部分逐渐变细。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2013162071A Semiconductor device and manufacturing method of the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2013162071A
公开(公告)日：2013-08-19
申请号：JP2012025042
申请日：2012-02-08
申请人： J Devices:Kk , 株式会社ジェイデバイス
发明人： SAWACHI SHIGENORI , YAMAGATA OSATAKE , INOUE KOJI , ITAKURA SATORU , CHIKAI TOMOYA , HORI MASAHIKO , KATSUMATA AKIO
IPC分类号： H01L25/065 , H01L25/07 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/49816 , H01L23/5384 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L24/97 , H01L25/50 , H01L2224/0401 , H01L2224/04105 , H01L2224/06135 , H01L2224/12105 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48145 , H01L2224/73265 , H01L2224/73267 , H01L2224/82031 , H01L2224/82039 , H01L2224/92244 , H01L2225/06524 , H01L2225/06548 , H01L2225/06562 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/1029 , H01L2225/1035 , H01L2924/12042 , H01L2924/12044 , H01L2924/15311 , H01L2924/00014 , H01L2924/00015 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which achieves downsizing by forming a plurality of semiconductor chips into a vertically-stacked structure; and to provide a semiconductor device manufacturing method in which the number of manufacturing processes is significantly reduced.SOLUTION: A semiconductor device comprises: a semiconductor element 2; a support substrate 1; an insulating material layer 4 for encapsulating the semiconductor element 2 and surroundings of the semiconductor element 2; a metal thin film wiring layer 6 provided in the insulating material layer 4 and a part of which is exposed on an outer surface; and a metal via 9 provided in the insulating material layer 4 and electrically connected to the metal thin film wiring layer 6. There is a plurality of numbers of semiconductor elements 2. Each semiconductor element 2 is stacked via an insulating material such that a circuit surface faces the metal thin film wiring layer 6 side. Electrode pads of each semiconductor element 2 are exposed without being shielded by another semiconductor element stacked thereon and electrically connected with the metal thin film wiring layer.
摘要翻译：要解决的问题：提供一种通过将多个半导体芯片形成为垂直堆叠结构来实现小型化的半导体器件; 并且提供其中制造工艺的数量显着减少的半导体器件制造方法。解决方案：半导体器件包括：半导体元件2; 支撑基板1; 用于封装半导体元件2和半导体元件2的周围的绝缘材料层4; 设置在绝缘材料层4中并且其一部分暴露在外表面上的金属薄膜布线层6; 以及设置在绝缘材料层4中并电连接到金属薄膜布线层6的金属通孔9.多个半导体元件2.多个半导体元件2通过绝缘材料堆叠，使得电路表面面向金属薄膜布线层6侧。每个半导体元件2的电极焊盘暴露而不被另一个堆叠在其上的半导体元件屏蔽，并与金属薄膜布线层电连接。

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