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1. 发明专利

JP2012114457A Printed wiring board 有权
标题翻译：印刷线路板
公开(公告)号：JP2012114457A
公开(公告)日：2012-06-14
申请号：JP2012023714
申请日：2012-02-07
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： ASAI MOTOO , INAGAKI YASUSHI , WANG DONGDONG , YAHASHI HIDEO , SHIRAI SEIJI
IPC分类号： H05K3/46
CPC分类号： H01L2924/15311 , H01L2924/15312 , H01L2924/19106
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board that has a built-in capacitor and appropriately connects with the built-in capacitor.SOLUTION: Chip capacitors 20 are housed in a core substrate 30. The chip capacitors 20 are electrically connected at first and second electrodes 21, 22 coated with copper plating films by means of copper-plated via holes 46. The copper plating films smooth the surfaces of the first and second electrodes 21, 22 and eliminate resin residues when blind holes are bored in connection layers 40 to increase the reliability of connection between the via holes 46 and the chip capacitors 20.
摘要翻译：要解决的问题：提供具有内置电容器并且适当地与内置电容器连接的印刷线路板。解决方案：芯片电容器20容纳在芯基板30中。片状电容器20通过镀铜通孔46在第一电极21和第二电极22电镀铜镀层。电镀铜膜使第一和第二电极21,22的表面平滑，并且当连接层40中的盲孔被钻孔时消除树脂残留物，以增加通孔46和片状电容器20之间的连接的可靠性。版权所有（C） 2012年，JPO＆INPIT

2. 发明专利

JP2009055059A Multi-layer printed wiring board having filled via structure 审中-公开
标题翻译：多层印刷线路板通过结构填充
公开(公告)号：JP2009055059A
公开(公告)日：2009-03-12
申请号：JP2008275258
申请日：2008-10-27
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： SHIRAI SEIJI , SHIMADA KENICHI , ASAI MOTOO
IPC分类号： H05K3/46 , H05K3/42
摘要： PROBLEM TO BE SOLVED: To provide a build-up multi-layer printed wiring board having filled-via structure and excellent in surface smoothness and reliability on connection.
SOLUTION: This multi-layer printed wiring board 1 is formed by laminating conductor circuits 11 and interlayer insulating resin layers each other. The interlayer insulating resin layer is provided with openings, and this opening is formed with a plate-filled via hole having a flat surface at the same surface height as other conductor circuits 11 positioned in the same layer. The conductor circuit 11 has thickness less than 1/2 of the via hole diameter, and further, a ratio of (the diameter of the via hole)/(thickness of the interlayer insulating resin layer) is set at 1-4.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有填充通孔结构的积层多层印刷线路板，并且在连接时具有优异的表面平滑性和可靠性。解决方案：该多层印刷电路板1通过层叠导体电路11和层间绝缘树脂层而形成。层间绝缘树脂层设置有开口，该开口形成有平板状的通孔，该通孔具有与位于同一层中的其它导体电路11相同的表面高度。导体电路11具有小于通孔直径的1/2的厚度，并且（通孔的直径）/（层间绝缘树脂层的厚度）的比率设定为1-4。版权所有（C）2009，JPO＆INPIT

3. 发明专利

JP2009076934A Multilayer printed wiring board and method of manufacturing multilayer printed wiring board 有权
标题翻译：多层印刷线路板及制造多层印刷线路板的方法
公开(公告)号：JP2009076934A
公开(公告)日：2009-04-09
申请号：JP2008310003
申请日：2008-12-04
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： SHIRAI SEIJI , SHIMADA KENICHI , ASAI MOTOO
IPC分类号： H05K3/46 , H05K1/11 , H05K3/40 , H05K3/42
摘要： PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board in which a board surface can be made flat and the delamination of an interlayer resin insulation layer is prevented. SOLUTION: The multilayer wiring board 10 keeps the flatness of the surface of the multilayer printed wiring board even if an upper layer via hole 70 is connected thereto because the surface of a lower layer via hole 50 is flat. The surface of the multilayer printed wiring board is made flat when resin for forming an interlayer resin insulation layer 60 is applied on the layer of a plane layer 53 in a manufacturing process because the resin is escaped into the recess 50a of a via hole 50A of the plane layer 53 and the thickness of the interlayer insulation layer 60 can be made uniform. Further, the interlayer resin insulation layer 60 is hardly peeled off (delaminated) because adhesion between the plane layer 53 and the upper layer of the interlayer resin insulation layer 60 is increased for the recess 50a of the via hole 50A formed at the plane layer 53 serves as an anchor. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供可以使板表面平坦化并且防止层间树脂绝缘层的分层的多层印刷线路板。解决方案：由于下层通孔50的表面是平坦的，所以多层布线板10即使连接上层通孔70也能保持多层印刷电路板的表面的平坦度。在制造过程中，由于树脂逸出到通孔50A的凹部50a中，因此在层叠树脂绝缘层60的形成树脂被施加到平面层53的层上时，将多层印刷电路板的表面平坦化可以使平面层53和层间绝缘层60的厚度均匀。此外，由于形成在平面层53的通孔50A的凹部50a，层间树脂绝缘层60的平面层53与上层之间的粘附性增加，层间树脂绝缘层60难以剥离（剥离）充当锚点。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2009177217A Method for manufacturing multi-layer printed wiring board 有权
标题翻译：制造多层印刷线路板的方法
公开(公告)号：JP2009177217A
公开(公告)日：2009-08-06
申请号：JP2009117373
申请日：2009-05-14
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： SHIRAI SEIJI , SHIMADA KENICHI , ASAI MOTOO
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a multi-layer printed wiring board capable of preventing warping from occurring and attaining high density. SOLUTION: Since via-holes 50, 70 and 90 are filled with a soldering material, an area of the interlayer resin insulating layer 60 disposed directly above the via-hole 50 of the lower interlayer resin insulating layer 40 can be made smooth. Thus, a conductor circuit 72 for connecting the via-hole 50 of the lower layer to the via-hole of the upper layer can be placed, at a position directly above the via-hole 50 which has been a dead space in a prior art, resulting in a high-density multi-layer printed wiring board. Moreover, since the via-holes 50, 70 and 90 are arranged in a crank shape, they are not localized. For this reason, the multi-layer printed wiring board 10 has property of preventing warpage from occurring therein, and superior mounting reliability in mounting IC chips, and the like, thereon. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：解决的问题：提供一种能够防止翘曲发生并实现高密度的多层印刷线路板的制造方法。解决方案：由于通孔50,70和90填充有焊接材料，所以可以使下层层间树脂绝缘层40的通孔50正上方的层间树脂绝缘层60的面积平滑。因此，用于将下层的通孔50连接到上层的通路孔的导体电路72可以放置在现有技术中已经是死空间的通路孔50正上方的位置，产生高密度多层印刷线路板。此外，由于通孔50,70和90布置成曲柄形，所以它们不是局部化的。因此，多层印刷电路板10具有防止翘曲发生的特性，在其上安装IC芯片等的优良的安装可靠性。版权所有（C）2009，JPO＆INPIT

5. 发明专利

JP2009038390A Method for manufacturing multilayer printed wiring board 审中-公开
标题翻译：制造多层印刷线路板的方法
公开(公告)号：JP2009038390A
公开(公告)日：2009-02-19
申请号：JP2008250777
申请日：2008-09-29
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： SHIRAI SEIJI , SHIMADA KENICHI , ASAI MOTOO
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To propose a method for manufacturing a multilayer printed wiring board having filled via structure and advantageous for forming a fine pattern.
SOLUTION: The multilayer printed wiring board includes alternately stacked conductor circuit and interlayer resin insulating layer. Manufacturing steps of the multilayer printed wiring board include at least the following (1)-(6) steps: (1) a step to form a lower layer conductor circuit on a substrate; (2) a step to form an interlayer resin insulating layer coating the lower layer conductor circuit, and to form an opening part to reach the lower layer conductor circuit; (3) a step to form a nonelectrolytic plated film on a surface of the interlayer resin insulating layer; (4) a step to form a plating resist; (5) a step to form a conductor layer by applying electrolytic plating; and (6) a step to remove the plating resist, and also to remove the nonelectrolytic plated film beneath the plating resist. Thickness of the upper layer conductor circuit is less than the half of the via hole diameter, and less than 25 μm.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提出一种具有填充通孔结构并有利于形成精细图案的多层印刷线路板的制造方法。解决方案：多层印刷线路板包括交替堆叠的导体电路和层间树脂绝缘层。多层印刷线路板的制造步骤至少包括以下（1） - （6）步骤：（1）在基板上形成下层导体电路的步骤; （2）形成涂覆下层导体电路的层间树脂绝缘层的步骤，形成到下层导体电路的开口部分; （3）在层间树脂绝缘层的表面形成非电解电镀膜的工序; （4）形成电镀抗蚀剂的工序; （5）通过电镀法形成导体层的步骤; 和（6）除去电镀抗蚀剂的步骤，以及除去电镀抗蚀剂下面的非电解镀膜。上层导体电路的厚度小于通孔直径的一半，小于25μm。版权所有（C）2009，JPO＆INPIT

6. 发明专利

JP2012033949A Printed wiring board and method of manufacturing the same 有权
标题翻译：印刷线路板及其制造方法
公开(公告)号：JP2012033949A
公开(公告)日：2012-02-16
申请号：JP2011214982
申请日：2011-09-29
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： ASAI MOTOO , INAGAKI YASUSHI , WANG DONG-DONG , YAHASHI HIDEO , SHIRAI SEIJI
IPC分类号： H05K3/46 , H01L23/12 , H05K3/32
CPC分类号： H01L2224/16225 , H01L2924/15312 , H01L2924/19105
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable printed wiring board in which loop inductance can be reduced.SOLUTION: In a printed wiring board 10 where resin insulation layers 144, 244 and conductor circuits 158, 258 are laminated on a core substrate 30 containing a capacitor 20, the core substrate 30 is constituted by laminating second and third core substrates 12U, 13D on and under a first core substrate 11 in which a through-hole 11A for containing the capacitor 20 is formed, the first, second and third core substrates 11, 12U, 13D are constituted by impregnating a core material with resin, the resin insulation layers 144, 244 are composed of a resin material not having a core material, a via hole 60 for connection with the electrodes 21, 22 of the capacitor 20 is formed in at least one of the second and third core substrates 12U, 13D, and electrical connection is taken between the via hole 60 and the electrodes 21, 22 of the capacitor 20.
摘要翻译：要解决的问题：提供可以降低回路电感的高度可靠的印刷线路板。解决方案：在包含电容器20的芯基板30上层压树脂绝缘层144,244和导体电路158,258的印刷电路板10中，芯基板30通过层叠第二和第三芯基板12U 在其中形成有用于容纳电容器20的通孔11A的第一芯基板11和下面的第一，第二和第三芯基板11,12U，13D通过用树脂浸渍芯材而构成，树脂绝缘层144,244由不具有芯材的树脂材料构成，用于与电容器20的电极21,22连接的通孔60形成在第二和第三芯基板12U，13D中的至少一个中，并且在通孔60和电容器20的电极21,22之间进行电连接。版权所有：（C）2012，JPO＆INPIT

7. 发明专利

JP2012099861A Printed wiring board 审中-公开
标题翻译：印刷线路板
公开(公告)号：JP2012099861A
公开(公告)日：2012-05-24
申请号：JP2012023713
申请日：2012-02-07
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： ASAI MOTOO , INAGAKI YASUSHI , WANG DONGDONG , YAHASHI HIDEO , SHIRAI SEIJI
IPC分类号： H05K3/46 , H01L23/12 , H05K1/18
CPC分类号： H01L2924/15311 , H01L2924/15312 , H01L2924/19106
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board which includes built-in capacitors, and can appropriately connect with the built-in capacitors.SOLUTION: Chip capacitors 20 are housed in a core substrate 30. The chip capacitors 20 are electrically connected to first and second electrodes 21 and 22 coated with a copper plating film 29 through via holes 46 plated with copper. The copper plating film 29 makes surfaces of the first and second electrodes 21 and 22 smooth and no resin residue is left when a non- through hole 43 is opened at a connection layer 40. This can improve connection reliability between the via holes 46 and the chip capacitors 20.
摘要翻译：要解决的问题：提供包括内置电容器的印刷电路板，并且可以适当地连接内置电容器。芯片电容器20容纳在芯基板30中。芯片电容器20通过镀铜的通孔46与连接有镀铜膜29的第一和第二电极21和22电连接。当在连接层40上打开非通孔43时，镀铜膜29使第一和第二电极21和22的表面光滑，并且不会残留树脂残留物。这可以提高通孔46和片式电容器20.版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2011135106A Method of manufacturing multilayer printed wiring board with filled via structure 有权
标题翻译：通过结构填充制造多层印刷线路板的方法
公开(公告)号：JP2011135106A
公开(公告)日：2011-07-07
申请号：JP2011082353
申请日：2011-04-04
申请人： Ibiden Co Ltd , イビデン株式会社
发明人： SHIRAI SEIJI , SHIMADA KENICHI , ASAI MOTOO
IPC分类号： H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a build-up multilayer printed wiring board which has a filled via structure, and is superior in surface smoothness and connection reliability.
SOLUTION: A method of manufacturing the multilayer printed wiring board by alternately laminating a conductor circuit and an interlayer insulating layer includes the processes of: forming an opening for a via hole in the interlayer insulating layer; forming an electroless plating film on a surface of the interlayer insulating film and an inner-wall surface of the opening; forming plating resist for forming the via hole and conductor circuit on the electroless plating film; and forming an electrolytic plating film at an opening of the plating resist to fill the opening, surrounded with the electroless plating film, with an electrolytic plating to thereby form the via hole having a flat surface and simultaneously to form the conductor circuit whose thickness is less than a half of a via hole diameter of the via hole, and also forming the surface of the via hole and the surface of the conductor circuit positioned in the same layer with the via hole at the same height.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有填充的通孔结构的积层多层印刷线路板，并且具有优异的表面平滑度和连接可靠性。解决方案：通过交替层叠导体电路和层间绝缘层来制造多层印刷线路板的方法包括以下过程：在层间绝缘层中形成用于通孔的开口; 在层间绝缘膜的表面和开口的内壁面上形成化学镀膜; 在化学镀膜上形成用于形成通孔和导体电路的电镀抗蚀剂; 并且在电镀抗蚀剂的开口处形成电解镀膜以填充由化学镀膜包围的开口，用电解电镀形成具有平坦表面的通孔，同时形成厚度较小的导体电路超过通孔的通孔直径的一半，并且还形成通孔的表面和位于与通孔相同高度的同一层中的导体电路的表面。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2002100873A PRINTED WIRING BOARD AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002100873A
公开(公告)日：2002-04-05
申请号：JP2000266285
申请日：2000-09-01
申请人： IBIDEN CO LTD
发明人： ASAI MOTOO , INAGAKI YASUSHI , O TOUTO , YAHASHI HIDEO , SHIRAI SEIJI
IPC分类号： H01G2/06 , H01G4/38 , H05K1/18 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a printed wiring board together with its manufacturing method for reduced loop inductance. SOLUTION: Chip capacitors 20 are provided in a printed wiring board 10 to shorten the distance between an IC chip 90 and the chip capacitors 20, reducing a loop inductance. The chip capacitors 20 are housed in a thick core substrate 30, so the printed wiring board is not required to be thicker.

10. 发明专利

JP2001332437A CAPACITOR AND MULTILAYERED PRINTED WIRING BOARD 失效
公开(公告)号：JP2001332437A
公开(公告)日：2001-11-30
申请号：JP2000148693
申请日：2000-05-19
申请人： IBIDEN CO LTD
发明人： YAHASHI HIDEO , SHIRAI SEIJI , ITO KATSUTOSHI
IPC分类号： H01G2/06 , H01G4/228 , H01L23/12 , H05K3/46
摘要： PROBLEM TO BE SOLVED: To provide a capacitor which is suitable for being housed or built in a multilayered printed wiring board. SOLUTION: A capacitor is housed or built in a multilayered printed wiring board, in which at least a part of its surface is roughened, an average roughness (Rj) of the roughened surface ranges from 0.01 to 5 μm, and the roughened surface is formed by embossing. Interlayer resin insulating layers and conductor circuits are formed successively on the board, in which the capacitor is housed or built for the formation of the multilayered printed wiring board, and the capacitor, the conductor circuit, and the upper and lower conductor circuit are connected through via holes.

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