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1. 发明专利

JPS61140280A Profile compensating circuit 失效
标题翻译：配置文件补偿电路
公开(公告)号：JPS61140280A
公开(公告)日：1986-06-27
申请号：JP26076784
申请日：1984-12-12
申请人： Hitachi Ltd , Hitachi Video Eng Co Ltd
发明人： KUBOTA SADAO , IKEDA KAZUHIRO , KURITA TOSHIYUKI
IPC分类号： H04N5/208
摘要： PURPOSE: To apply profile compensation to a titled profile as well as vertical profile compensation to fine patterns and a sharp angle portion by selecting a 1H delay time in a vertical profile compensation filter as 1H
+ τs (τs is a subcarrier half period time).
CONSTITUTION: A video brightness signal (signal (a) at a sampling point) inputted to an input terminal 1 is inputted to an adder circuit 4 and a 1H+τs delay line 2. The output signal of the line 2 is a signal (b), which is inputted to an adder circuit 5, a subtraction circuit 6 and a 1H+τs delay line 3, the output signal of which is a signal (c), it is inputted to an adder circuit 4. The adder circuit 4 outputs a signal of picture element signal (a) + picture element signal (c), the signal is inputted to the subtraction circuit 6, where the arithmetic of [2 × picture element signal (b) - picture element signal (a) - picture element signal (c) = output of subtraction circuit 6] is executed to extract a profile signal. The signal is inputted to an adder circuit 13. In this case, the quantity of profile compensation is adjusted by adjusting the profile signal by gain control.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过在垂直轮廓补偿滤波器中选择1H延迟时间作为1H taus（taus是子载波半周期时间），将轮廓补偿应用于标题轮廓以及垂直轮廓补偿，以精细图案和锐角部分）。构成：输入到输入端1的视频亮度信号（采样点的信号（a））输入到加法电路4和1H +延迟线2.线2的输出信号是信号（b ）输入到加法器电路5，减法电路6和1H + taus延迟线3，其输出信号是信号（c），它被输入到加法器电路4.加法器电路4输出像素信号（a）+图像元素信号（c）的信号，该信号被输入到减法电路6，其中[2×像素信号（b） - 像素信号（a） - 像素执行信号（c）=减法电路6的输出]以提取分布信号。信号被输入到加法器电路13.在这种情况下，通过增益控制来调整轮廓信号来调整轮廓补偿量。

2. 发明专利

JPH09275546A WIDE CONVERSION CIRCUIT FOR IMAGE SIGNAL, DIGITAL BROADCAST RECEIVER AND TELEVISION RECEIVER 失效
公开(公告)号：JPH09275546A
公开(公告)日：1997-10-21
申请号：JP8392196
申请日：1996-04-05
申请人： HITACHI LTD
发明人： SUGIYAMA MASAHITO , HIRANO YASUHIRO , KOJIMA NOBORU , TERANISHI KENTARO , KUBOTA SADAO , NISHISETO TAKAAKI , KASAHARA YASUHIRO , NAKAGAKI NOBUFUMI
IPC分类号： H04N5/46 , H04N7/01
摘要： PROBLEM TO BE SOLVED: To provide the wide conversion circuit for an image signal in which wide conversion processing with less image quality deterioration is realized and a TV image with high image quality is obtained. SOLUTION: Motion correction interlace - noninterlace scanning conversion is conducted based on a motion vector for MPEG video coding with respect to a decoded image signal of digital broadcast and wide conversion signal processing such as vertical compression and vertical expansion is conducted by using the noninterlace scanning signal. Then the noninterlace scanning signal or the signal converted again into the interlace scanning signal is used to generate a signal suitable for a display section whose aspect ratio is 16:9 or 4:3.

3. 发明专利

JPH09247612A HANDLING METHOD FOR IMAGE SIGNAL 失效
公开(公告)号：JPH09247612A
公开(公告)日：1997-09-19
申请号：JP5440096
申请日：1996-03-12
申请人： HITACHI LTD
发明人： HIRANO YASUHIRO , HOSHINO TAKASHI , KOJIMA NOBORU , SUGIYAMA MASAHITO , TERANISHI KENTARO , KUBOTA SADAO , KASAHARA YASUHIRO , TAKAHASHI SATOSHI
IPC分类号： G06F17/30 , H04N5/44 , H04N5/91
摘要： PROBLEM TO BE SOLVED: To obtain the handling method and device for an image signal with excellent convenience performance by conducting level adaptive edit processing in response to a level set by the user for a digest edit or a program edit or the like. SOLUTION: A handling device for an image signal is made up of a video audio demodulation section 1, a compression section 2, a data bank 3, an expansion section 4, an aid code detection section 5, and a function setting section 6. The image handling aid information is configured to be a hierarchical structure with plural levels from a level 1 of the highest importance to a level N of the lowest importance layer depending on importance of information contents of a video signal. The user sets a level of a layer among the plural levels and conducts a library edit to extract a still image of a video signal and to record it, a digest edit to extract a signal for a specific period of the video signal and to record it, or a program edit to record a signal of a specific program of the video signal or the like according to the set level. That is, the technological means for level adaptive edit processing is employed for the method.

4. 发明专利

JPH09163264A DISPLAY DEVICE FOR TELEVISION SIGNAL 失效
公开(公告)号：JPH09163264A
公开(公告)日：1997-06-20
申请号：JP32601295
申请日：1995-12-14
申请人： HITACHI LTD
发明人： FURUHATA TAKASHI , KATAOKA HIROSHI , KUBOTA SADAO
IPC分类号： H04N5/46 , H04N7/01
摘要： PROBLEM TO BE SOLVED: To display a television signal whose scanning number of lines is nearly twice that of a standard television signal by using a same deflection system while eliminating image quality disturbance attended with display of a television signal with a few scanning line numbers. SOLUTION: A standard television signal received from an input terminal 1 is converted into a display signal whose field frequency and frame frequency are respectively nearly twice those of the standard television signal and whose displayed scanning line number is nearly twice that of the standard television signal by a signal conversion circuit 10. Furthermore, a pulse generating circuit 22 of the signal conversion circuit 10 generates a synchronizing signal with respect to the display signal based on synchronizing information of the standard television signal and the display signal is displayed on a display device 50 by allowing the display device 50 to use a deflection system 42 thereby conducting deflection scanning at a horizontal scanning frequency nearly twice that of the standard television signal.

5. 发明专利

JPH04243395A VIDEO SIGNAL PROCESSING CIRCUIT FOR DIGITAL TELEVISION RECEIVER 失效
公开(公告)号：JPH04243395A
公开(公告)日：1992-08-31
申请号：JP1564691
申请日：1991-01-17
申请人： HITACHI LTD
发明人： KAIZAKI KAZUHIRO , MATONO TAKAAKI , HARATANI ATSUSHI , KUBOTA SADAO
IPC分类号： H04N9/44 , H04N9/77
摘要： PURPOSE:To reduce the effect of noise by allowing a standard/non-standard detection circuit to extract a synchronizing signal and a color burst signal from a luminance signal and a chrominance signal from a comb-line filter so as to discriminate the standard/non-standard input signal. CONSTITUTION:A comb-line filter 102 separates an inputted composite video signal into a luminance signal and a chrominance carrier signal and a color demodulation circuit 106 demodulates the chrominance carrier signal into a color difference signal, which is outputted. Moreover, a line lock PLL 120 extracts a synchronizing signal from the video signal from the filter 102, generates and outputs the synchronized line clock. Furthermore, a burst lock PLL 119 extracts a color burst signal from the video signal inputted from a terminal 101 and generates and outputs a synchronized burst lock clock. Then a standard/non-standard detection circuit 121 based on them decides whether or not the inputted video signal satisfies the NTSC system and decides it to be the standard signal when satisfied and it to be the non-standard signal when not satisfied.

6. 发明专利

JPS6175674A Noise reducing circuit 失效
标题翻译：噪音减少电路
公开(公告)号：JPS6175674A
公开(公告)日：1986-04-18
申请号：JP19664884
申请日：1984-09-21
申请人： Hitachi Ltd
发明人： KAIZAKI KAZUHIRO , KUBOTA SADAO , HARADA HIROSHI , MATSUURA SHIGEO
IPC分类号： H04N5/21 , H04N9/64
CPC分类号： H04N5/21
摘要： PURPOSE: To preserve resolution almost completely and to reduce a noise sufficiently by selecting plural video signals used for signal processing simultaneously from near the video signal to be processed, installing a outline detecting circuit of a picture and controlling an attenuating coefficient in a signal attenuating circuit suitably.
CONSTITUTION: At delay circuits 5 and 6, an average value signal of output video signals 12 and 13, for which 2S and H-S only is respectively delayed, is outputted from an average value circuit 7. Next, a difference signal between the average value signal and an input video signal 11 inputted from an input terminal 1 is outputted from a substracter circuit 2. In an outline detecting circuit 8 in accordance with the fact whether or not the outline is detected between the input video signal 11 and an output video signal 12 in which 2S only is in the past, and between the input video signal 11 and an output video signal 13 for which H-S only is in the past, after the difference signal, which is multiplied by k (0≤k
摘要翻译：目的：几乎完全地保持分辨率，并通过从待处理的视频信号附近同时选择用于信号处理的多个视频信号来充分降低噪声，安装图像的轮廓检测电路并控制信号衰减电路中的衰减系数适当地构成：在延迟电路5和6中，从平均值电路7输出输出视频信号12和13的平均值信号，其中2S和HS仅分别被延迟。接下来，平均值信号并且从输入端子1输入的输入视频信号11从减法电路2输出。在轮廓检测电路8中，根据在输入视频信号11和输出视频信号12之间是否检测到轮廓的事实其中2S仅在过去，并且在输入视频信号11和HS仅在过去的输出视频信号13之后，在乘以k（0 <= k <1）的差分信号之后，在信号衰减电路3中，在加法器电路4中将信号加到输入视频信号11上，从视频信号输出端9去除具有小噪声的视频信号。输出视频信号被同时输入到延迟电路5和6，并且重复相同的操作。

7. 发明专利

JPS547231A POWER SOURCE DEVICE FOR TELEVISION RECEIVER 失效
公开(公告)号：JPS547231A
公开(公告)日：1979-01-19
申请号：JP7222277
申请日：1977-06-20
申请人： HITACHI LTD
发明人： KUBOTA SADAO
IPC分类号： H04N5/63
摘要： PURPOSE:To secure an assured start as well as to reduce the power loss at the steady operation time, by increasing the discharge time constant obtained through the parallel location of the impedance element and the horizontal exciting circuit as well as selecting the low supply voltage to the level near the minimum voltage to excite the horizontal output circuit.

8. 发明专利

JP2564300B2 失效
公开(公告)号：JP2564300B2
公开(公告)日：1996-12-18
申请号：JP8880887
申请日：1987-04-13
申请人： HITACHI LTD
发明人： SHINOSAWA MEGUMI , NAKAGAKI NOBUFUMI , HARADA HIROSHI , KUBOTA SADAO
IPC分类号： H03K3/356 , H03K3/037

9. 发明专利

JPH06283978A DYNAMIC TYPE SET/RESET FLIP-FLOP 失效
公开(公告)号：JPH06283978A
公开(公告)日：1994-10-07
申请号：JP3107694
申请日：1994-03-01
申请人： HITACHI LTD
发明人： SHINOSAWA MEGUMI , NAKAGAKI NOBUFUMI , KUBOTA SADAO
IPC分类号： H03K3/037 , H03K3/356
摘要： PURPOSE:To provide a dynamic type flip-flop capable of performing set and reset. CONSTITUTION:A clocked CMOS NOR gate 20 at a first stage inputs data DIN and a Set signal, and introduces and outputs the NOR of them synchronizing with a clock pulse phi inputted separately. A clocked CMOS NOR gate 30 at a second stage inputs an output signal DIN from the clocked CMOS NOR gate 20 at the first stage and a Reset signal, and introduces the NOR of them synchronizing with a pulse phi with negative phase for the clock pulse phi inputted separately, and outputs it as an output signal DOUT. When inputted Set signal and Reset signal show high levels, they are not set, and are reset preferentially, and a signal of low level is outputted from the clocked CMOS NOR gate 30 at the second stage as the output signal DOUT.

10. 发明专利

JPH0329585A MOVEMENT DETECTION CIRCUIT 失效
公开(公告)号：JPH0329585A
公开(公告)日：1991-02-07
申请号：JP16477389
申请日：1989-06-27
申请人： MITSUBISHI ELECTRIC CORP , HITACHI LTD
发明人： YAMAGUCHI NORIYUKI , YAO SEIJI , SUZUKI YOSHITERU , SHIBATA TATSUO , NAKAGAWA HIMIO , KUBOTA SADAO , KAIZAKI KAZUHIRO
IPC分类号： H04N9/77
摘要： PURPOSE:To attain the movement adaptive processing by obtaining only movement quantity of a color signal through the calculation of a frame unit from a correlation detection output depending on a difference of 2 frames or over of a color demodulation signal. CONSTITUTION:A 2-frame difference obtained by a 2-frame difference detection circuit 40 is subject to one frame sum at a 1 frame sum detection circuit 50 comprising a 1 frame delay circuit 20 and an adder 21, a high frequency component of a Y signal in the 2-frame difference is eliminated and only the 2-frame difference of the C signal is obtained. Moreover, the Y signal modulated by a low pass filter(LPF) 17 is eliminated and the result is a movement detection output 107 of the C signal through an absolute value circuit 18 and a nonlinear conversion circuit 19 and outputted from an output terminal 12. Thus, the modulated Y signal component is eliminated from a V signal subject to color demodulation by a C signal pass filter and movement detection of an accurate C signal is attained.

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