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JP2003346500A Semiconductor integrated circuit and its test method 审中-公开
标题翻译：半导体集成电路及其测试方法
公开(公告)号：JP2003346500A
公开(公告)日：2003-12-05
申请号：JP2002155107
申请日：2002-05-29
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： TAKAZAWA YOSHIO , YAMADA TOSHIO , YANAGISAWA KAZUMASA , HAYASAKA TAKASHI
IPC分类号： G01R31/28 , G06F12/16 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/26 , H01L31/0328
CPC分类号： G11C29/26 , G11C2029/1806 , G11C2029/2602 , G11C2029/3202
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit wherein a memory test efficiency on a plurality of on-chip memories by using a march pattern or the like is enhanced. SOLUTION: The semiconductor integrated circuit is provided with a plurality of bridge circuits (21 to 25) that convert test data information from a common test bus (31) connected to a plurality of memories (11 to 15) the access data width and the address decode logic of which differ from each other into access data width unique to each memory, convert test address information from the common test bus into a bit arrangement unique to each memory, and supply the result to each corresponding memory. It is possible to test a plurality of the memories in parallel by supplying the test address information from the common test bus to a plurality of the memories in parallel. It is possible to unify address scanning directions of the respective memories with respect to the test address information in a particular direction according to the bit arrangement unique to each memory by supplying the test data information to a plurality of the memories with the different access data widths in parallel. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种半导体集成电路，其中通过使用行进模式等提高了对多个片上存储器的存储器测试效率。解决方案：半导体集成电路设置有多个桥接电路（21至25），其将来自连接到多个存储器（11至15）的公共测试总线（31）的测试数据信息转换为访问数据宽度并且其地址解码逻辑彼此不同成为每个存储器唯一的访问数据宽度，将测试地址信息从公共测试总线转换成每个存储器唯一的位排列，并将结果提供给每个对应的存储器。通过将来自公共测试总线的测试地址信息并行地提供给多个存储器，可以并行地测试多个存储器。通过将测试数据信息提供给具有不同访问数据宽度的多个存储器，可以根据每个存储器唯一的位排列将特定方向上的各个存储器的地址扫描方向相对于测试地址信息进行统一在平行下。版权所有（C）2004，JPO

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