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1. 发明专利

JPS61259342A SIMULATING SYSTEM OF PRIVILEGED INSTRUCTION IN VIRTUAL COMPUTER SYSTEM 失效
公开(公告)号：JPS61259342A
公开(公告)日：1986-11-17
申请号：JP9958485
申请日：1985-05-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MAYA YUZURU , TSUTSUI SHIGECHIKA , MIURA AKIYOSHI , UMENO HIDENORI , NISHIMUKAI TADAHIKO , KAWASAKI IKUYA
IPC分类号： G06F11/26 , G06F9/46
摘要： PURPOSE:To improve the simulation of a privileges instruction by providing a hardware register to show the head address of the privileged instruction at the central processing device of a virtual computer. CONSTITUTION:When a virtual computer 20 issues the privileged instruction, the control is shifted to a virtual computer supporting mechanism 21, the head address of the privileged instruction is stored into the privileged instruction register, the address of the next privileged instruction is stored into the stack and the control is shifted to a virtual computer control program 22. Finally, the virtual computer control program 22 simulates the privileged instruction.

2. 发明专利

JPS61210439A TRACING CONTROL SYSTEM FOR TASK 失效
公开(公告)号：JPS61210439A
公开(公告)日：1986-09-18
申请号：JP5050385
申请日：1985-03-15
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： AOKI HISANOBU , TSUTSUI SHIGECHIKA
IPC分类号： G06F9/48 , G06F11/28 , G06F11/36
摘要： PURPOSE:To trace a designated task only without giving an influence to other task by setting the debugging task, executing the embedding operation of an inequality instruction, stopping and restarting the target task by the inequality instruction interruption, and executing the trace processing. CONSTITUTION:A debugger task 2-3 is set, and the program prepared by the secondary operating system 2-2 is loaded as an on-line task. Next, the break command name, the target task number and the head address to execute the tracing are inputted from a console 2-4. When the task 2-3 receives the break command, the command is analyzed, the inequality instruction is set to the designating address and the task 2-3 has the inequality instruction interruption. At such a time, the contents of the address embedding the designating task number and inequality instruction and the address before embedding the inequality instruction are stored at the register. When the inequality instruction interruption occurs, the break stop is executed, the task 2-3 waits for the command, the command to execute the tracing is inputted from the console 2-4 and the tracing processing is executed.

3. 发明专利

JPS5164335A shukiokusochihogohoshiki 失效
标题翻译： SHUKIOKUSOCHIHOGOHOSHIKI
公开(公告)号：JPS5164335A
公开(公告)日：1976-06-03
申请号：JP9359372
申请日：1972-09-20
申请人： Hitachi Ltd
发明人： TSUTSUI SHIGECHIKA , KURAMIZU MASARU , IDE TOSHIKI , MURAKAMI MASAAKI
IPC分类号： G06F12/14 , G06F11/00 , G06F12/00 , G06F12/02 , G06F13/00 , G06F15/16 , G06F15/17 , G11C29/00

4. 发明专利

JPS6220035A CONTROL SYSTEM FOR VIRTUAL COMPUTER SYSTEM 失效
公开(公告)号：JPS6220035A
公开(公告)日：1987-01-28
申请号：JP15824985
申请日：1985-07-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： TSUTSUI SHIGECHIKA , MIURA AKIYOSHI , UMENO HIDENORI , NISHIMUKAI TADAHIKO , KAWASAKI IKUYA
IPC分类号： G06F9/46
摘要： PURPOSE:To make it possible to accept always interruption during execution of a virtual computer VM by accepting interruption in an actual computer independently of the execution level which a status register Sr of the actual computer indicates when interruption from the external occurs during execution of the VM. CONSTITUTION:When the control is transferred from a virtual computer control program (VMCP) to the VM, a flag VMFLG indicating execution of the VM is set, and AND between its NOT signal and each flag indicating the execution level in the Sr of the actual computer is operated to convert the execution level to '0'. Since execution level '0' is the effective execution level of the actual computer in this computer, the execution level of the actual computer is '0' during execution of the VM and interruption of each level can be accepted.

5. 发明专利

JPS61259343A INTERRUPTION FACTOR EVACUATING SYSTEM OF VIRTUAL COMPUTER 失效
公开(公告)号：JPS61259343A
公开(公告)日：1986-11-17
申请号：JP9958585
申请日：1985-05-13
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： YOKOHATA SHIZUO , MIURA AKIYOSHI , TSUTSUI SHIGECHIKA , UMENO HIDENORI , NISHIMUKAI TADAHIKO , KAWASAKI IKUYA
IPC分类号： G06F9/46 , G06F9/48
摘要： PURPOSE:To execute a multiple interruption processing by loading successively the program information to the stack when the interruption occurs. CONSTITUTION:When interruption occurs, a virtual computer mode flag 31 is checked, and it is investigated whether the executed program is a virtual computer system or a control program. In case of the virtual computer system, a flag 31 is zero, a vector table 34 designated by a pointer register 32 and a stack 38 designated by a stack pointer 36 are converted to the one for the control program, and the control is shifted to the address of the control program shown by the contents of the interruption vector table. When the control program is being executed, the information during the execution of the control program is loaded to a stack 37 and the control is shifted to the address shown by the contents of the vector table corresponding to the interruption.

6. 发明专利

JPS61184642A INTERRUPTION PROCESSING SYSTEM 失效
公开(公告)号：JPS61184642A
公开(公告)日：1986-08-18
申请号：JP2462585
申请日：1985-02-12
申请人： HITACHI LTD
发明人： MAEDA TAKAO , TSUTSUI SHIGECHIKA , SUGITA YUMIKO , YAMAKI KAZUSHI
IPC分类号： G06F9/48 , G06F9/46
摘要： PURPOSE:To shorten an interruption prohibiting time by executing the pre- processing part only by the processing device when the interruption occurs, describing the information necessary for the after-processing to an FIFO register and thereafter, executing the after-processing part when the interruption prohibiting condition is released. CONSTITUTION:A processing part 1-1 divides the interruption information inputted into the pre-processing part related directly to the external interruption and necessary to execute in the interruption prohibiting condition, and the after-processing part except it. A processing part 11 executes the pre-processing part only when the interruption occurs, the information necessary to the after- processing part is described in an FIFO register 1-9, and after the multiple interruption is cancelled at the time of dispatching, the interruption prohibition is released by lowering the interruption level to the level of the task, and by reading the information from the register 1-9, the after-processing part is executed.

7. 发明专利

JPS51101436A 失效
公开(公告)号：JPS51101436A
公开(公告)日：1976-09-07
申请号：JP2593575
申请日：1975-03-05
申请人： HITACHI LTD
发明人： TSUTSUI SHIGECHIKA , KURAMIZU MASARU , KAMIUCHI TOSHIRO , HIRAI KOJI , HORI JUTARO
IPC分类号： G06F9/48

8. 发明专利

JPS61184644A CONTROL SYSTEM OF VIRTUAL COMPUTER SYSTEM 失效
公开(公告)号：JPS61184644A
公开(公告)日：1986-08-18
申请号：JP2463085
申请日：1985-02-12
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MIURA AKIYOSHI , TSUTSUI SHIGECHIKA , UMENO HIDENORI , NISHIMUKAI TADAHIKO , KAWASAKI IKUYA
IPC分类号： G06F9/46 , G06F12/10
摘要： PURPOSE:To minimize the correction and the addition of the program by using the register of the computer control program, starting the program of the virtual computer, and returning the program of the virtual computer during the execution through the register to the virtual computer control program. CONSTITUTION:When an EXVM instruction to start the program of a virtual computer VM is issued from a computer control program VMCP, at a CPU, the contents of the stack pointer 18 of a control register, a vector space register 19 are respectively saved to a save 1 register 22 and a save 2 register 23. Next, the value is loaded from a VM block table on the memory shown by a VM block pointer 21 to the pointer 18 and the register 19, and to the program of the VM, the control is shifted. When the interruption occurs while the program of the VM is executed, at the CPU, the contents of the pointer 18 and the register 19 are saved to the table. Next, the value saved to the save 1 register 22 and the save 2 register 23 is respectively loaded to the pointer 18 and the register 19 and the control is shifted to the interruption processing of the VMCP.

9. 发明专利

JPS61160147A VIRTUAL COMPUTER CONTROL SYSTEM 失效
公开(公告)号：JPS61160147A
公开(公告)日：1986-07-19
申请号：JP16244184
申请日：1984-07-31
申请人： HITACHI LTD
发明人： SUGITA YUMIKO , TSUTSUI SHIGECHIKA , MAEDA TAKAO , YABE EIICHI
IPC分类号： G06F9/46
摘要： PURPOSE:To discriminate individual operation systems (OSs) even if the trap number to be used by respective OSs are the same, and to execute a trap instruction properly by forming a means for discriminating an OS to which a trap instruction is generated and a trap interruption vector table or a trap number conversion table registering only the address of each trap processing in each OS. CONSTITUTION:A flag indicating the OS executing a task at present is set up in a blank area of a system byte of a status register. Consequently, the OS to which the trap is generated can be discriminated. When the flag is '1', a secondary OS is defined by using a bit 11 e.g. The trap interruption vector table is used for applying an address for proper trap processing to each secondary OS. The contents correspondingly assigned to trap numbers 0-15 in a table heading are the processing addresses of 16 trap instructions generated to a certain OS.

10. 发明专利

JPS61143858A FILE SHARE METHOD FOR PLURAL OPERATING SYSTEMS 失效
公开(公告)号：JPS61143858A
公开(公告)日：1986-07-01
申请号：JP26547884
申请日：1984-12-18
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MAYA YUZURU , MIURA AKIYOSHI , TSUTSUI SHIGECHIKA
IPC分类号： G06F12/00 , G06F9/46
摘要： PURPOSE:To facilitate easy sharing of a file with computers which are actuated by a center OS (operating system) and a secondary OS by securing such a constitution where the task of the center OS can use the file control function of the secondary OS as it is. CONSTITUTION:A computer system consists of a center OS11, a task 12 of the center OS and a secondary OS13d connected to a bus respectively. A task 14f of the OS13 requests the use of a file for a specific task of the OS13 when it wants the use of a file which is under the control of the OS13. A task 14 of the secondary OS received the request issues a file use request to the secondary OS13. Thus the task 14 requests the use of the file to the OS13. Then the task of the OS11 uses directly the file under the control of the OS13.

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