专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JP2003258107A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 审中-公开
公开(公告)号：JP2003258107A
公开(公告)日：2003-09-12
申请号：JP2002053238
申请日：2002-02-28
申请人： HITACHI LTD
发明人： MINAMI MASATAKA , HASHIMOTO NAOTAKA
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To form a capacitor of high reliability in an analog circuit. SOLUTION: After a wiring trench is formed, by sequentially dry-etching an oxide silicon film 22 and a nitride silicon film 21 which are formed on a semiconductor substrate 1, a titanium nitride film and a W film are deposited in the order, on the semiconductor substrate 1 including the inside of the wiring trench, and the wiring trench is filled with the W film. By eliminating the titanium nitride film and the W film, which are positioned outside the wiring trench by a CMP method, and a wiring 25 is formed. After a silicon nitride film 27 and a titanium nitride film 28 are deposited in the order on the semiconductor substrate 1, by patterning the titanium nitride film 28, a capacitor MIM is formed wherein the wiring 25 is set as a lower electrode, the silicon nitride film 27 is made a capacity insulating film and the titanium nitride film 28 is set as an upper electrode. COPYRIGHT: (C)2003,JPO

2. 发明专利

JPH0927552A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0927552A
公开(公告)日：1997-01-28
申请号：JP17524095
申请日：1995-07-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUKUDA KAZUJI , YOSHIDA YASUKO , HOSHINO YUTAKA , HASHIMOTO NAOTAKA , ASAYAMA MASAICHIRO , KOIDE MASAKI , YOSHIZUMI KEIICHI , OKAMOTO ERI , HAGA SATORU , IKEDA SHUJI
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To prevent the characteristic of a substrate (well) power-feeding part from deteriorating by constituting a power-feeding part for feeding a specific potential to a semiconductor substrate of a conductive-type semiconductor region with a higher impurity concentration than that of the semiconductor substrate. SOLUTION: In an SRAM, the source and drain regions respectively of p- channel-type MISFETQs and n-channel-type MISFET of the peripheral circuit of MISFETQd1 and Qd2 for driving a memory cell and MISFETQt1 and Qt2 for carrying the memory cell are constituted in LDD substructure. Then, a third semiconductor region which is in different conductive type from that of a semiconductor region and has a higher impurity concentration than a well is formed at the lower portion of the semiconductor region with a low impurity concentration for constituting one portion of the source and drain regions. At this time, the bottom portion of the third semiconductor region is made nearly the same depth as that of the semiconductor region with a high impurity concentration for constituting the other one portion of the source and drain regions.

3. 发明专利

JPH08162543A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08162543A
公开(公告)日：1996-06-21
申请号：JP30529794
申请日：1994-12-09
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUJITA ERI , YOSHIDA YASUKO , FUKUDA KAZUJI , YOSHIZUMI KEIICHI , HOSHINO YUTAKA , ASAYAMA MASAICHIRO , HASHIMOTO NAOTAKA , HASHIMOTO CHIEMI
IPC分类号： H01L27/11 , H01L21/8244
摘要： PURPOSE: To improve operational stability of a memory cell in a semiconductor integrated circuit device with a memory cell of a two-layer gate electrode structure. CONSTITUTION: When an SRAM of a two-layer gate electrode structure formed by forming gate electrodes 14a1, 14a2, 14b1, 14b2 of each of driver MOS/FETs 2Q1, 2Q2 and transfer MOS/FETs 2Q3, 2Q4 constituting a memory cell 2a of an SRAM in different layers is formed, the gate electrodes 14b1, 14b2 of the transfer MOS/FETs 2Q3, 2Q4 are formed and thereafter the gate electrodes 14a1, 14a2 of the driver MOS/FETs 2Q1, 2Q2 are formed.

4. 发明专利

JPH0595113A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH0595113A
公开(公告)日：1993-04-16
申请号：JP25347191
申请日：1991-10-01
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , OOKI NAGATOSHI , ISHIDA HIROSHI
IPC分类号： H01L29/78
摘要： PURPOSE:To provide a MIS-type field effect transistor having high reliability and high current driving ability and is proper for high integration. CONSTITUTION:A source and a drain have an LDD structure, a sidewall spacer 6 is provided to an area near the sidewall of a gate electrode above a low concentration diffusion layer 2 thereof, a gate electrode bottom part protrudes and a gate electrode protruding part is buried inside a semiconductor substrate 1 in a self-alignment manner. Thereby, it is possible to bury an overlapping part of the low concentration diffusion layer 2 and a gate electrode 5 inside the silicon substrate 1 in a self-alignment manner and to realize a semiconductor device having high reliability and high current driving ability through the plane occupied area of a transistor is small. Furthermore, contact between the transistor and an upper wiring layer can be formed in a self-alignment manner and a plane occupied area of the transistor can be further reduced.

5. 发明专利

JPH04320036A SEMICONDUCTOR DEVICE AND ITS MANUFACTURE 失效
公开(公告)号：JPH04320036A
公开(公告)日：1992-11-10
申请号：JP8654791
申请日：1991-04-18
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , JINRIKI HIROSHI , NAKADA MASAYUKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI
IPC分类号： H01L21/314 , H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/10 , H01L27/108 , H01L27/11 , H01L29/78 , H01L29/786
摘要： PURPOSE:To provide a semiconductor device having MISFETs suitable for high reliability and high current driving capacity. CONSTITUTION:A source/drain has an LDD structure provided with a high- dielectric side wall spacer 6 in a vicinity of the gate electrode side wall on top of a low-doped diffusion layer 2, and with another tunneling thin film insulating film 7 between the side wall spacer and the diffusion layer 2. A gate fringe field effect to the diffusion layer 2 is improved, and hot carrier deterioration special to the LDD structure is made hard to occur; therefore, improvement in reliability of field relaxation and improvement in current driving power can be realized simultaneously.

6. 发明专利

JPH03218667A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH03218667A
公开(公告)日：1991-09-26
申请号：JP28705990
申请日：1990-10-26
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , SHIMIZU AKIHIRO
IPC分类号： G11C11/412 , G11C11/419 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To decrease a memory cell in area and electric power consumption by a method wherein two drive MOSFETs and two transfer MOSFETs are specified in length and width of channel, and the current of an active load FET is set 1X10 A or above in intensity. CONSTITUTION:N channel drive MOSFETs 3 and 4 are set to be WDEFF and LDEFF respectively in effective length and width of channels, and N channel transfer MOSFETs 5 and 6 are set WTEFF and LTEFF respectively in effective length and width of channels. The memory cell ratio (WDEFF/LDEFF)/WTEFF/LTEFF is set smaller than 3. That is, when data is read out from a cell, as polysilicon TFTs 1 and 2 functioning as active loads through which an ON-current larger than 1X10 can be made to flow are used as memory cells, the memory cell ratio can be made smaller than 3 and the effective channel length WDEFF can be made small. By this setup, a memory cell be made small in occupying area.

7. 发明专利

JPH0374848A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH0374848A
公开(公告)日：1991-03-29
申请号：JP21008289
申请日：1989-08-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHIMIZU AKIHIRO , YAMANAKA TOSHIAKI , HASHIMOTO NAOTAKA , HASHIMOTO KOJI , ISHIBASHI KOICHIRO , SASAKI KATSURO , SHIMOHIGASHI KATSUHIRO , TAKEDA EIJI
IPC分类号： H01L29/78 , H01L21/336
摘要： PURPOSE:To obtain an MISFET having a source.drain with low diffusion area which can be used as a basic device after 0.3mum process by forming a high concentration impurity region of the same conductivity type as the substrate in the substrate surface under an element isolating region. CONSTITUTION:A first element isolating insulating film 3 is formed on a first channel stopper layer 2 on a silicon substrate 1. Then, after a gate oxide film 4, a gate electrode 5, a silicon oxide film 6 are formed, an impurity for an n-layer is implanted to form a side wall spacer 6. Next, a side wall spacer 22 of a silicon nitride film is formed, and after boron is implanted, a second element isolating oxide film 8 is formed. At that time, a high concentration impurity layer 7 due to the boron is formed under the film 8 to constitute a second channel stopper layer. Then, the spacer 22 is removed and an opening 23 for source.drain connection is formed by self-alignment. A 0.3mum level MISFET can easily be formed in accordance with this construction.

8. 发明专利

JPH02172273A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02172273A
公开(公告)日：1990-07-03
申请号：JP32582588
申请日：1988-12-26
申请人： HITACHI LTD
发明人： MEGURO SATOSHI , UCHIBORI KIYOBUMI , SUZUKI NORIO , MOTOYOSHI MAKOTO , KOIKE ATSUYOSHI , YAMANAKA TOSHIAKI , SAKAI YOSHIO , HONJO SHIGERU , MINATO OSAMU , KAGA TORU , HASHIMOTO NAOTAKA , HASHIMOTO KOJI
IPC分类号： H01L27/01 , H01L21/8244 , H01L27/00 , H01L27/11
摘要： PURPOSE:To increase the freedom of memory cell layout by arranging the gate electrode of an MISFET for load on the upper part of the gate electrode of an MISFET for driving, and arranging source drain and channel regions of the MISFET for load on the upper part of the gate electrode of the MISFET for load. CONSTITUTION:In the memory cell of a CMOS type SRAM MISFET's Qp1, Qp2 for load are arranged on the upper part of MISFET's Qd1, QD2 for driving. The MOSFET's for load have gate electrodes 34 different from gate electrodes 27 of the MISFET's for driving. As a result, source.drain and channel regions 37A-37C of the MISFET's Qp1, Qp2 for load can be laid out almost without restrictions to the gate electrodes 27 of the MISFET's Qd1, Qd2 for driving. Thereby the freedom of memory cell layout can be increased.

9. 发明专利

JPH01114072A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01114072A
公开(公告)日：1989-05-02
申请号：JP27015187
申请日：1987-10-28
申请人： HITACHI LTD
发明人： HASHIMOTO NAOTAKA , YAMANAKA TOSHIAKI , SAKAI YOSHIO
IPC分类号： H01L21/8244 , H01L27/11
摘要： PURPOSE:To increase stored charge and to improve soft error resistance due to alpha rays by forming a capacity element of a conductive film, which forms a high resistance element, and a conductive film of the upper layer so as to supply charge to a memory cell. CONSTITUTION:High resistance elements 7d, 7e, a power supply wire 7c and the lower part electrodes 7a and 7b of a capacity element are constituted by a conductive film of the third layer so as to be connected to the sources 3c and 3d of the transfer MOS transistors T3 and T4 through the connection holes 14a and 14b formed on an interlayer film 10 of a conductive film of the first and second layers, and on an interlayer insulating film 20 of the conductive films of the second and third layers so as to form a conductive film 15 and a capacity element of the fourth layer further through an insulating film 30. By this constitution, stored charge of a memory cell is increased and a soft error caused by alpha rays in company with micronization can be prevented from increasing.

10. 发明专利

JPH01114071A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH01114071A
公开(公告)日：1989-05-02
申请号：JP27014387
申请日：1987-10-28
申请人： HITACHI LTD
发明人： HASHIMOTO NAOTAKA , YAMANAKA TOSHIAKI , SAKAI YOSHIO
IPC分类号： G11C11/41 , H01L21/8244 , H01L27/11
摘要： PURPOSE:To reduce a required area of a memory cell by making a region, where the driving MOS transistor sources are fixed to earth potential, a conductive film for being formed on the upper part of the main surface of a semiconductor substrate. CONSTITUTION:The source 3g and 3h are connected to the MOS transistors T1 and T2 through a conductive film 13c on the second layer being mutually connected through the connection holes 12c and 12d of an interlayer insulating film 10, while the conductive film 13c on the second layer is fixed to earth potential so as to be connected to the sources of all driving MOS transistors. Further, the conductive films 13a and 13b on the second layer are connected to the drains 3a and 3b of the transfer MOS transistors T3 and T4 through the connection holes 12a and 12b, further, the conductive films 13a and 13b are connected to the aluminium electrodes 2a and 2b of a data wire through the connection holes 4a and 4b so as to reduce an area of a memory cell.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式