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1. 发明专利

JPS6122237A Apparatus for inspecting appearance of object 失效
标题翻译：检查对象外观的装置
公开(公告)号：JPS6122237A
公开(公告)日：1986-01-30
申请号：JP10373985
申请日：1985-05-17
申请人： Hitachi Ltd
发明人： NAKAGAWA KIYOSHI , KAGEYAMA JIYOUICHIROU , EGUCHI KAZUHIKO , NAKAJIMA SHIGEAKI
IPC分类号： G01N21/88 , G01B11/24 , G01N21/956 , G03F1/84 , H01L21/027 , H01L21/66
CPC分类号： G01N21/95607
摘要： PURPOSE:To enhance the reliability of inspection while making it possible to perform high speed inspection, by comparing pattern information, which formed the basis of the fabrication of a mask pattern, with the mask pattern. CONSTITUTION:The reference pattern from a magnetic tape 18 storing an information signal showing a pattern to be baked to a photomask is two-dimensionally regenerated in memory 9 while converted to a binary signal and, at the same time, a mask pattern to be inspected is regenerated in memory 8 and both signals are compared in a comparing circuit. If the mask pattern to be inspected has a flaw 19, the contents of the memories 8, 9 come to non-coincidence at the part corresponding to the position where the flaw is present to generate a non-coincident signal. Whereupon, a measuring machine detects the coordinates where said flaw is present and the coordinates signal is processed by CPU to be displayed on a recording display part as data. By this method, the confirmation of the flaw existence can be performed rapidly.
摘要翻译：目的：为了提高检查的可靠性，通过将形成掩模图案的基础的图案信息与掩模图案进行比较，可以进行高速检查。构成：存储将要烘烤的图案的信息信号的光盘18的参考图案在存储器9中二维地再生，同时被转换为二进制信号，同时将要检查的掩模图案在存储器8中再生，并且在比较电路中比较两个信号。如果要检查的掩模图案具有缺陷19，则存储器8,9的内容在与存在缺陷的位置相对应的部分处不一致，以产生非重合信号。因此，测量机器检测出存在所述缺陷的坐标，并且由CPU处理坐标信号以在记录显示部件上显示作为数据。通过这种方法，可以快速地进行缺陷存在的确认。

2. 发明专利

JPS5542013A AUTOMATIC APPEARANCE TEST SYSTEM 失效
公开(公告)号：JPS5542013A
公开(公告)日：1980-03-25
申请号：JP11464378
申请日：1978-09-20
申请人： HITACHI LTD
发明人： HAMADA TOSHIMITSU , EGUCHI KAZUHIKO
IPC分类号： G01N21/88 , G01B11/24 , G01N21/93 , G01N21/956 , G06K9/62 , G06T1/00 , H01L21/027 , H01L21/302 , H01L21/66
摘要： PURPOSE:To make it possible to automatically change test area of an object in such a way that control data for whole object and variety distinction data stored in memory device which has stored data for generating standard pattern are selected therefrom by selector circuit. CONSTITUTION:Object image signal derived from photographing device 9 and standard pattern from standard pattern generator 7 are compared by discriminator circuit 10, as standard pattern is generated synchronously to scanning operation for X-Y stage. Stored in memory 5 are 4 data comprising test area designation data, band-like area designation data, standard pattern generating data, and data indicating terminal of data, and information which insicates attribute of each data. The standard pattern generating data is transferred to pattern generating section 7 for each band-like area separately, and system controlling data from memory 5 is transferred to system control section 8 at each time when test is started and when scanning operation for band-like area is terminated. Therefore, change of scanning area for each test can be facilitated, and control thereof can be automized.

3. 发明专利

JPS52116051A BIT PATTERN GENERATING METHOD OF TWO DIMENTIONAL ORTHOGONAL PATTERN AN D ITS UNIT 失效
公开(公告)号：JPS52116051A
公开(公告)日：1977-09-29
申请号：JP3252476
申请日：1976-03-26
申请人： HITACHI LTD
发明人： OKAMOTO KEIICHI , NAKAGAWA KIYOSHI , EGUCHI KAZUHIKO
IPC分类号： G06T11/20 , G06T7/00
摘要： PURPOSE:To reduce the scale of the hardware reproducing the pattern, by describing the pattern with least data, in describing the coordinates of the comparing inspection pattern to the recording media.

4. 发明专利

JP2002092055A METHOD FOR DESIGNING LOGIC CIRCUIT, SYSTEM FOR SUPPORTING DESIGN OF LOGIC CIRCUIT AND COMPUTER READABLE RECORDING MEDIUM 失效
公开(公告)号：JP2002092055A
公开(公告)日：2002-03-29
申请号：JP2000279734
申请日：2000-09-14
申请人： HITACHI LTD
发明人： MIYAZAKI HIROSHI , EGUCHI KAZUHIKO , TANIMOTO MASAAKI
IPC分类号： G06F9/06 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To shorten a time by optimizing logic synthesis for logic circuit description in a hardware description language. SOLUTION: The optimization algorithm candidates of a plurality of circuit blocks given in logic circuit description in the hardware description language are decided by considering the humming distances of the circuit blocks (S1-S3). Then, the circuit blocks in which the optimization algorithm candidates decided by the first processing are made common are grouped by considering the level of connection of the circuit blocks (S4-S6). The result of the grouping is obtained for the circuit blocks whose characteristics are clear in terms of the algorithm candidates or the level of connection, and there are remaining circuit blocks whose characteristics are unclear. Then, the result of the grouping is reflected on the initial state, and the grouping of the plurality of circuit blocks is optimized by a genetic algorithm so that the optimization of the grouping of the circuit blocks whose characteristics are unclear can be promoted (S7-S13).

5. 发明专利

JPH02217965A METHOD AND DEVICE FOR FORMING DIAGRAM 失效
公开(公告)号：JPH02217965A
公开(公告)日：1990-08-30
申请号：JP3822689
申请日：1989-02-20
申请人： HITACHI LTD
发明人： MURATA NORIKO , YOKOTA TAKAYOSHI , HAMADA KANMAN , EGUCHI KAZUHIKO
IPC分类号： G06F17/50 , G06T11/00
摘要： PURPOSE:To make it possible to easily observe a logic diagram or the like by dividing a reference element into plural blocks in accordance with prescribed contents, moving these blocks based upon a moving rule determining relation among blocks and arranging the blocks having the common contents as a group. CONSTITUTION:This device is constituted of a block information input device 11, a diagram output device 12, a reference arrangement processing part 14, an arrangement correcting processing part 15 and an arrangement correction rule storing part 16. After executing reference arrangement, the blocks having mutual relation at their contents are grouped and extracted by using only the information to be a few keys, a rule is prepared in accordance with each group and the diagram is partially corrected. Thereby, the group of similar blocks can be processed by the same processing and the group can be reflected to a diagram without decoding a function in detail. In the formation of various diagrams capable of plotting reference elements in each block in addition to a logic diagram, the diagrams to be easily grasped and observed by a user can be displayed and outputted.

6. 发明专利

JPS5242790A METHOD OF INSPECTING APPEARANCE OF OBJECTS 失效
公开(公告)号：JPS5242790A
公开(公告)日：1977-04-02
申请号：JP11770775
申请日：1975-10-01
申请人： HITACHI LTD
发明人： NAKAGAWA KIYOSHI , KAGEYAMA NAGAICHIROU , EGUCHI KAZUHIKO , NAKAJIMA SHIGEAKI
IPC分类号： G01N21/88 , G01B11/24 , G01B21/20 , G01N21/956
摘要： PURPOSE:Appearance of an object, such as photomask, is inspected with the pattern information which is the basis for preparation of master patterns as a refere reference, whereby the degree of reliability of the inspection is enhanced and the speed of inspection is increased.

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