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1. 发明专利

JP2006190240A Information processor 有权
标题翻译：信息处理器
公开(公告)号：JP2006190240A
公开(公告)日：2006-07-20
申请号：JP2005130746
申请日：2005-04-28
申请人： Hitachi Information Technology Co Ltd , Hitachi Ltd , 株式会社日立インフォメーションテクノロジー , 株式会社日立製作所
发明人： NAKATANI MORIHIDE , FUJIWARA SHISEI , ISHIKI TOSHIHIRO , SAKUMA NAOTO , FUNATSU JUNICHI , YOSHIDA TAKESHI , ITOI TOMONAGA
IPC分类号： G06F15/173 , G06F12/08
CPC分类号： G06F15/17337
摘要： PROBLEM TO BE SOLVED: To provide a server device having scale-up scalability with SMP joint between a plurality of blade server modules in addition to scale-out scalability of a conventional blade server system. SOLUTION: A node controller in each blade server module has a SMP joint interface, and it is joined via a back plane. A link between the blade server modules is isometrically wired on the back plane, and a loop is also wired in each blade server module at a length equal to that of the link between the blade server modules on the back plane for synchronizing operation. A reference clock distribution unit is mounted on the back plane for distributing a reference clock to the blade server modules. The reference clock is switched by a clock distribution circuit in each blade server module, thereby permitting the synchronization of the reference clock for the SMP-joint blade server modules. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：除了常规刀片服务器系统的扩展可扩展性之外，还提供具有在多个刀片服务器模块之间的SMP联合的具有放大可扩展性的服务器设备。解决方案：每个刀片服务器模块中的节点控制器具有SMP接口接口，并通过背板连接。刀片服务器模块之间的链接在背面平面上等距连接，并且每个刀片服务器模块中的线圈连接线的长度等于后平面上的刀片服务器模块之间的链接的长度，用于同步操作。参考时钟分配单元安装在背板上，用于将参考时钟分配给刀片服务器模块。参考时钟由每个刀片服务器模块中的时钟分配电路切换，从而允许SMP关节刀片服务器模块的参考时钟的同步。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2007233499A Information processor 审中-公开
标题翻译：信息处理器
公开(公告)号：JP2007233499A
公开(公告)日：2007-09-13
申请号：JP2006051486
申请日：2006-02-28
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SEKI TATSUICHIRO , FUJIWARA SHISEI
IPC分类号： G06F15/173
摘要： PROBLEM TO BE SOLVED: To enable an SMP (symmetric multiprocessor)system including a perfect mesh type node-to-node connection constituted by a passive backplane to use a network which is unused in a configuration of less than a maximum node number without making a change to the passive backplane. SOLUTION: In the information processor to be operated as a symmetric multiprocessor system with a predetermined number of nodes mounted on a backplane, in which wires for mutually connecting the predetermined number of nodes in a perfect mesh topology are arranged on the backplane, when the processor is operated as the symmetric multiprocessor system with nodes of a number smaller than the predetermined number being mounted on the backplane, a jumper board is mounted in a position where no node is mounted, and the wires in the backplane which are unconnected with nodes are connected by wires in the jumper board. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了实现包括由无源背板构成的完美网格类型节点到节点连接的SMP（对称多处理器）系统以使用在小于最大节点数的配置中未使用的网络而无需更改无源底板。解决方案：在要作为对称多处理器系统操作的信息处理器中，具有安装在背板上的预定数量的节点，其中用于将完美网状拓扑中的预定数量的节点相互连接的导线布置在背板上，当处理器作为具有小于预定数量的节点的对称多处理器系统被安装在背板上时，跳线板被安装在没有安装节点的位置，并且背板中的电线未被连接到节点通过电线连接在跳线板中。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2009140376A Multiprocessor computer system with snoop filter divided into specific address ranges 审中-公开
标题翻译：具有SNOOP过滤器的多处理器计算机系统分配到特定地址范围
公开(公告)号：JP2009140376A
公开(公告)日：2009-06-25
申请号：JP2007317850
申请日：2007-12-10
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： JONO YUTARO , TAKASE RYO , FUJIWARA SHISEI
IPC分类号： G06F12/08
摘要： PROBLEM TO BE SOLVED: To solve the problem of a multiprocessor system that since a cache state information is registered in one snoop filter, dependence on the access frequency of a specific address area occurs, resulting in deterioration of performance address areas other than the specific address area.
SOLUTION: A plurality of snoop filters corresponding to a designated address area are constituted. With a read request to a main memory as a trigger, the address and the cache state of each cache memory are registered to only a snoop filter corresponding to a requested cache line address. In snoop address filters corresponding to the address areas other than the specific address area, ejection of the cache state information due to access of the specific address area and re-access of the ejected address no longer occurs.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题为了解决由于在一个监听滤波器中登记了高速缓存状态信息而导致的特定地址区域的访问频率的依赖性的多处理器系统的问题，导致除了具体地址区域。解决方案：构成与指定地址区对应的多个窥探滤波器。通过对主存储器的读取请求作为触发器，每个高速缓冲存储器的地址和高速缓存状态仅被注册到与所请求的高速缓存行地址相对应的窥探过滤器。在与特定地址区域以外的地址区域相对应的探测地址过滤器中，不再发生由于访问特定地址区域而导致的高速缓存状态信息的退出。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2010009628A Server system 有权
标题翻译：服务器系统
公开(公告)号：JP2010009628A
公开(公告)日：2010-01-14
申请号：JP2009237839
申请日：2009-10-15
申请人： Hitachi Information & Communication Engineering Ltd , Hitachi Ltd , 日立情報通信エンジニアリング株式会社 , 株式会社日立製作所
发明人： NAKATANI MORIHIDE , FUJIWARA SHISEI , ISHIKI TOSHIHIRO , SAKUMA NAOTO , FUNATSU JUNICHI , YOSHIDA TAKESHI , ITOI TOMONAGA
IPC分类号： G06F15/173
摘要： PROBLEM TO BE SOLVED: To provide a server system which has, in addition to extensibility of scale-out type of a conventional blade server system, extensibility of scale-up type by making SMP (Symmetric Multi Processing) coupling among a plurality of blade server modules. SOLUTION: A node controller in each blade server module has an SMP coupling interface, and is coupled via a back plane. Links among individual blade server modules are laid through equidistant wiring lines on a back plane and besides a loop wiring line having length equal to that of the links among the individual blade server modules on the back plane is also laid in each blade server module, thereby setting up synchronization. Each blade server module has a reference clock distribution unit mounted on the back plane and adapted to distribute reference clocks and by switching reference clocks by a clock distribution circuit inside each blade server module, synchronization of reference clocks for SMP coupled blade server modules can be established. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种服务器系统，除了通常的刀片式服务器系统的扩展型扩展性之外，还可以通过在多个（多个）刀片服务器系统中进行SMP（对称多重处理）的刀片服务器模块。
解决方案：每个刀片服务器模块中的节点控制器具有SMP耦合接口，并通过背板耦合。单个刀片服务器模块之间的链接通过背板上的等距布线铺设，并且除了在每个刀片服务器模块中还布置了长度等于背板上各个刀片服务器模块之间的链路长度的环路布线设置同步。每个刀片服务器模块具有安装在背板上的参考时钟分配单元，并且适用于分配参考时钟，并通过每个刀片服务器模块内的时钟分配电路切换参考时钟，可以建立用于SMP耦合的刀片服务器模块的参考时钟的同步。版权所有（C）2010，JPO＆INPIT

5. 发明专利

JP2009282917A Interserver communication mechanism and computer system 审中-公开
标题翻译： INTERSERVER通信机制和计算机系统
公开(公告)号：JP2009282917A
公开(公告)日：2009-12-03
申请号：JP2008136943
申请日：2008-05-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TAKASE AKIRA , JONO YUTARO , FUJIWARA SHISEI
IPC分类号： G06F15/173
CPC分类号： H04L67/06
摘要： PROBLEM TO BE SOLVED: To eliminate the need for preparing an external I/O device for performing interserver communication for every physical server, and to prevent overhead due to protocol conversion from occurring.
SOLUTION: An interserver communication mechanism 161 is connected to an I/O link 201 and a plurality of physical servers via an I/O switch not shown in the figure. The interserver communication mechanism 161 has a read command generation part 203 for issuing a command to access data in the respective physical servers and a write command generation part 204 for transmitting read data to another server. Data are red from a data transmitter inside the interserver communication mechanism 161, the read data are written out to a data transmission destination as they are, and the data are directly returned in the interserver communication mechanism 161, so that data are mutually transferred between the physical servers.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了避免准备用于为每个物理服务器执行interserver通信的外部I / O设备的需要，并且防止由于协议转换而发生的开销。解决方案：服务器间通信机构161经由图中未示出的I / O开关连接到I / O链路201和多个物理服务器。服务器间通信机构161具有用于发出访问各个物理服务器中的数据的命令的读取命令生成部分203和用于将读取数据发送到另一个服务器的写入命令生成部分204。数据从服务器间通信机制161内的数据发送器发送红色，读取的数据被原样写入到数据发送目的地，并且数据在服务器间通信机制161中直接返回，使得数据在物理服务器。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2006018489A Memory interleaving system between a plurality of nodes 审中-公开
标题翻译：大量节目之间的记忆交互系统
公开(公告)号：JP2006018489A
公开(公告)日：2006-01-19
申请号：JP2004194565
申请日：2004-06-30
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIYATA TAKASHI , YAGI NOBUO , FUJIWARA SHISEI
IPC分类号： G06F12/06
CPC分类号： G06F12/0607
摘要： PROBLEM TO BE SOLVED: To provide a memory interleaving system between a plurality of nodes by which highly flexible node expansion and memory constitution can be attained.
SOLUTION: A destination register is prepared in a chip set 302 and a node on which a memory to be accessed is mounted is decided. Node information is set in the destination register and the destination register is selected by a physical address to be accessed to decide the node on which the memory to be accessed is mounted. Since the destination register is set, the size of load for memory access can be changed by the node. By setting an optimum destination register in accordance with the number of nodes 323 to be added and the capacity/transfer speed of memories, the throughput of memory access of respective nodes can be uniformed at high flexibility.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供在多个节点之间的存储器交错系统，由此可以实现高度灵活的节点扩展和存储器结构。解决方案：在芯片组302中准备目的地寄存器，并且确定其上安装有要访问的存储器的节点。在目的地寄存器中设置节点信息，并通过待访问的物理地址来选择目的地寄存器，以决定要在其上安装要访问的存储器的节点。由于目标寄存器被设置，存储器访问的负载大小可以被节点改变。通过根据要添加的节点323的数量和存储器的容量/传送速度设置最佳目的地寄存器，可以高度灵活地将各节点的存储器访问吞吐量均匀化。版权所有（C）2006，JPO＆NCIPI

7. 发明专利

JP2003030048A Multi-processor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：JP2003030048A
公开(公告)日：2003-01-31
申请号：JP2001217647
申请日：2001-07-18
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MORITA SHINICHIRO , SHIBATA MASABUMI , NAKAJIMA ATSUSHI , FUJIWARA SHISEI
IPC分类号： G06F12/08 , G06F15/16 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To easily extend the line size of a cache memory without being restricted by transfer size functioning as a unit to transmit/receive the data of a main memory via a coupling means of a multi-processor system in which cache memories are alternately connected with processors.
SOLUTION: The line size is set to be n times (n is an integer ≥2) the transfer size, and a processor module issues a coherent read request to request the data to the processor module and a memory module when a data request issued by a processor in the processor module causes a miss in cache read in the present cache memory and further issues a non-coherent read request to request the data only to the memory module for (n-1) times.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了容易地扩展高速缓冲存储器的行大小，而不受作为用于通过多处理器系统的耦合装置发送/接收主存储器的数据的传输大小的限制，其中高速缓冲存储器是与处理器交替连接。解决方案：线路大小被设置为传输大小的n倍（n是整数> = 2），并且当发出数据请求时，处理器模块发出相干读取请求以请求数据给处理器模块和存储器模块由处理器模块中的处理器引起高速缓存中的未命中读取，并且进一步发出非相干读请求，以仅将数据请求到存储器模块（n-1）次。

8. 发明专利

JP2011180933A I/o switch and computer system equipped with the same 审中-公开
标题翻译： I / O开关和计算机系统配套
公开(公告)号：JP2011180933A
公开(公告)日：2011-09-15
申请号：JP2010046072
申请日：2010-03-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： JONO YUTARO , TAKASE AKIRA , FUJIWARA SHISEI
IPC分类号： G06F15/173 , G06F9/54 , G06F11/20 , G06F13/10 , G06F15/17
摘要： PROBLEM TO BE SOLVED: To solve the problem that transfer performance is deteriorated because when data on the memory of one physical server have to be copied in the memory of two or more physical servers, using a general-purpose I/O interface which does not respond to multicast data transfer requires to issue a data write instruction to each of the plurality of physical servers, which results in increase in traffic between a server-to-server communication mechanism and an I/O switch. SOLUTION: The I/O switch is provided with a mechanism which comprises a register capable of holding a plurality of pieces of destination information in the control register of the server-to-server communication mechanism, and the register, when sending data to a plurality of destinations, capable of adding the plurality of pieces of destination information to the data to transfer data toward a plurality of destinations by the data write instruction of one time. The I/O switch shapes the data write instruction issued by the server-to-server communication mechanism to data write instructions to each of the destinations and simultaneously issues the data write instructions to the plurality of destinations. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了解决传输性能恶化的问题，因为当一个物理服务器的存储器上的数据必须被复制到两个或更多个物理服务器的存储器中时，使用通用I / O接口其不响应多播数据传输需要向多个物理服务器中的每一个发出数据写入指令，这导致服务器到服务器通信机制和I / O交换机之间的业务量增加。解决方案：I / O开关具有一种机构，其包括能够在服务器到服务器通信机制的控制寄存器中保存多条目的地信息的寄存器，并且当发送数据时，该寄存器到多个目的地，能够通过一次的数据写入指令将多条目的地信息添加到该数据以向多个目的地传送数据。 I / O开关将由服务器到服务器通信机制发出的数据写入指令形成为每个目的地的数据写入指令，同时向多个目的地发出数据写入指令。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JPH08328960A CACHE MEMORY DEVICE 失效
公开(公告)号：JPH08328960A
公开(公告)日：1996-12-13
申请号：JP13153095
申请日：1995-05-30
申请人： HITACHI LTD
发明人： FUJIWARA SHISEI , SHIBATA MASABUMI
IPC分类号： G06F12/08 , G06F12/12
摘要： PURPOSE: To considerably reduce overhead caused by an exchange operation at the time of cache error. CONSTITUTION: A cache memory is composed of four memory mats 5 of ways 0-4. A bypass buffer 10 holds contents to be copied in because of the last cache error. When the cache error is discriminated, a copy-in operation and a copy-out operation are parallelly executed by the memory mats 5 of mutually different ways. Concerning the copy-in operation, the contents of the bypass buffer 10 are written in the line of the way 0 where a margin is generated by ejecting data at the time of the last cache error. Concerning the copy-out operation, copy-out is executed by selecting the way 1, for example, excepting for the way 0 as a way candidate to eject data in the case of this cache error. The contents to be copied in at this time of cache error are written from a main storage device 14 to the bypass buffer 10.

10. 发明专利

JP2003150573A MULTIPROCESSOR SYSTEM 审中-公开
公开(公告)号：JP2003150573A
公开(公告)日：2003-05-23
申请号：JP2001345530
申请日：2001-11-12
申请人： HITACHI LTD
发明人： MORITA SHINICHIRO , FUJIWARA SHISEI , KOYANAGI MASARU , MURAKAMI SHIYOUKI
IPC分类号： G06F12/08 , G06F15/16 , G06F15/173 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To realize a correct cashe coherency consistent control, and to prevent sinking of processing even when executing readin processing of data from a main memory when a plurality of cashe memories nearly to each other in time. SOLUTION: When requiring the cashe coherency consistent control caused by the readin of the data for the cashe memories of the other node, an address of the data is held in a request control table, and when a cashe coherency consistent control request from the other cashe competes with this address, a cashe coherency consistent control result for requiring stopping and reexecution (a retry) of the readin of the data is answered. The cashe coherency consistent control result for requiring the retry is held in a starvation control part, and when the cashe memories execute the reexecution of the readin of the data, the other cashe memory restrains the readin of the data to the address.

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