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1. 发明专利

JP2010009628A Server system 有权
标题翻译：服务器系统
公开(公告)号：JP2010009628A
公开(公告)日：2010-01-14
申请号：JP2009237839
申请日：2009-10-15
申请人： Hitachi Information & Communication Engineering Ltd , Hitachi Ltd , 日立情報通信エンジニアリング株式会社 , 株式会社日立製作所
发明人： NAKATANI MORIHIDE , FUJIWARA SHISEI , ISHIKI TOSHIHIRO , SAKUMA NAOTO , FUNATSU JUNICHI , YOSHIDA TAKESHI , ITOI TOMONAGA
IPC分类号： G06F15/173
摘要： PROBLEM TO BE SOLVED: To provide a server system which has, in addition to extensibility of scale-out type of a conventional blade server system, extensibility of scale-up type by making SMP (Symmetric Multi Processing) coupling among a plurality of blade server modules. SOLUTION: A node controller in each blade server module has an SMP coupling interface, and is coupled via a back plane. Links among individual blade server modules are laid through equidistant wiring lines on a back plane and besides a loop wiring line having length equal to that of the links among the individual blade server modules on the back plane is also laid in each blade server module, thereby setting up synchronization. Each blade server module has a reference clock distribution unit mounted on the back plane and adapted to distribute reference clocks and by switching reference clocks by a clock distribution circuit inside each blade server module, synchronization of reference clocks for SMP coupled blade server modules can be established. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种服务器系统，除了通常的刀片式服务器系统的扩展型扩展性之外，还可以通过在多个（多个）刀片服务器系统中进行SMP（对称多重处理）的刀片服务器模块。
解决方案：每个刀片服务器模块中的节点控制器具有SMP耦合接口，并通过背板耦合。单个刀片服务器模块之间的链接通过背板上的等距布线铺设，并且除了在每个刀片服务器模块中还布置了长度等于背板上各个刀片服务器模块之间的链路长度的环路布线设置同步。每个刀片服务器模块具有安装在背板上的参考时钟分配单元，并且适用于分配参考时钟，并通过每个刀片服务器模块内的时钟分配电路切换参考时钟，可以建立用于SMP耦合的刀片服务器模块的参考时钟的同步。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2007094470A Method of hotplugging information processing apparatus 审中-公开
标题翻译：信息处理装置的方法
公开(公告)号：JP2007094470A
公开(公告)日：2007-04-12
申请号：JP2005279145
申请日：2005-09-27
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUZUKI SHINICHI , OKAZAWA KOICHI , ITOI TOMONAGA , TSUBOI YOSHIYUKI
IPC分类号： G06F13/10 , G06F9/445
摘要： PROBLEM TO BE SOLVED: To eliminate the possibility that users make errors during a process by automatically making the determinations required for hotplugging an information processing apparatus wherein a plurality of CPU blades share an I/O module. SOLUTION: If OSs on all the CPU blades 20, 21, 22 installed are hotplug-enabled when the I/O module 30 is hotplug-enabled, the I/O module 30 can be hotplugged. Even if the OSs on some of the CPU blades are not hotplug-enabled, the hotplugging is possible provided their power supply is off. Further, even if some of the CPU blades are not installed, the hotplugging is possible provided the other CPU blades installed satisfy the above requirements. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了消除用户在处理期间通过自动进行热插拔其中多个CPU刀片共享I / O模块的信息处理设备所需的确定的可能性。解决方案：当I / O模块30启用热插拔功能时，如果所有安装的所有CPU刀片20,21,22上的操作系统启用热插拔，则可以热插拔I / O模块30。即使某些CPU刀片上的操作系统不支持热插拔，只要电源关闭，热插拔即可。此外，即使没有安装一些CPU刀片，只要安装的其他CPU刀片满足上述要求，就可以进行热插拔。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006190240A Information processor 有权
标题翻译：信息处理器
公开(公告)号：JP2006190240A
公开(公告)日：2006-07-20
申请号：JP2005130746
申请日：2005-04-28
申请人： Hitachi Information Technology Co Ltd , Hitachi Ltd , 株式会社日立インフォメーションテクノロジー , 株式会社日立製作所
发明人： NAKATANI MORIHIDE , FUJIWARA SHISEI , ISHIKI TOSHIHIRO , SAKUMA NAOTO , FUNATSU JUNICHI , YOSHIDA TAKESHI , ITOI TOMONAGA
IPC分类号： G06F15/173 , G06F12/08
CPC分类号： G06F15/17337
摘要： PROBLEM TO BE SOLVED: To provide a server device having scale-up scalability with SMP joint between a plurality of blade server modules in addition to scale-out scalability of a conventional blade server system. SOLUTION: A node controller in each blade server module has a SMP joint interface, and it is joined via a back plane. A link between the blade server modules is isometrically wired on the back plane, and a loop is also wired in each blade server module at a length equal to that of the link between the blade server modules on the back plane for synchronizing operation. A reference clock distribution unit is mounted on the back plane for distributing a reference clock to the blade server modules. The reference clock is switched by a clock distribution circuit in each blade server module, thereby permitting the synchronization of the reference clock for the SMP-joint blade server modules. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：除了常规刀片服务器系统的扩展可扩展性之外，还提供具有在多个刀片服务器模块之间的SMP联合的具有放大可扩展性的服务器设备。解决方案：每个刀片服务器模块中的节点控制器具有SMP接口接口，并通过背板连接。刀片服务器模块之间的链接在背面平面上等距连接，并且每个刀片服务器模块中的线圈连接线的长度等于后平面上的刀片服务器模块之间的链接的长度，用于同步操作。参考时钟分配单元安装在背板上，用于将参考时钟分配给刀片服务器模块。参考时钟由每个刀片服务器模块中的时钟分配电路切换，从而允许SMP关节刀片服务器模块的参考时钟的同步。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2006293460A Fiber channel switching device, information processing system, and login processing method 有权
标题翻译：光纤通道切换装置，信息处理系统和登录处理方法
公开(公告)号：JP2006293460A
公开(公告)日：2006-10-26
申请号：JP2005109536
申请日：2005-04-06
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YASUDA YOSHIKO , KUME SHOJI , ITOI TOMONAGA
IPC分类号： G06F3/06 , G06F13/10
CPC分类号： H04L49/357 , H04L41/00 , H04L49/65
摘要： PROBLEM TO BE SOLVED: To miniaturize a server connected to a fibre channel switching device. SOLUTION: The fibre channel switching device to which a server and a storage device are connected, is characterized by being equipped with; a host controller which is connected with the server and controls a fibre channel protocol; a management table holding a hardware address of the host controller; a switching section for routing information of the fibre channel protocol; and a management section which manages the host controller and the switching section. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：使与光纤通道切换装置连接的服务器小型化。
解决方案：连接服务器和存储设备的光纤通道切换设备的特征在于配备有：主机控制器，与服务器连接并控制光纤通道协议; 保存主机控制器的硬件地址的管理表; 用于路由光纤信道协议信息的切换部分; 以及管理主机控制器和切换部分的管理部分。版权所有（C）2007，JPO＆INPIT

5. 发明专利

JP2002032266A INFORMATION PROCESSOR 失效
公开(公告)号：JP2002032266A
公开(公告)日：2002-01-31
申请号：JP2000217169
申请日：2000-07-18
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TAMURA TERUHITO , ITOI TOMONAGA , HIRAOKA TORU
IPC分类号： G06F12/10 , G06F9/35
摘要： PROBLEM TO BE SOLVED: To realize shortening of address conversion processing time and address mode switching time in an information processor to provide a large scale virtual address (LVA) space and an access register(AR) space. SOLUTION: An invalidation processing in the case of switching modes is unnecessitated by adding a mode bit (LVM) to discriminate which of segment table designation(STD) generated by large scale virtual address conversion or the one generated by access register conversion is held by the entries to the respective entries of an LVLB/ALB shared buffer 1000 to share a large scale virtual address conversion buffer (LVLB) and an access register conversion buffer (ALB) and of an LV/AR shared STD storage part 600 to store copy of the LVLB/ALB shared buffer 1000, comparing the LVM and the present address mode (L) of a PSW 200 and performing HIT detection.

6. 发明专利

JP2001014160A INFORMATION PROCESSOR 失效
公开(公告)号：JP2001014160A
公开(公告)日：2001-01-19
申请号：JP18837299
申请日：1999-07-02
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HIRAOKA TORU , ITOI TOMONAGA , HAKAMATA MASASHI
IPC分类号： G06F9/38 , G06F9/30
摘要： PROBLEM TO BE SOLVED: To advance a pipeline processing by reducing delay due to a branch- destination instruction read by requesting a memory to read the branch- destination instruction of a branch instruction to an instruction buffer when the branch instruction is decoded. SOLUTION: At an IF stage, instructions set in BIRP 400 and BIRS 500 are decoded by a 1st instruction decoder 900. When a branch instruction is decoded by the 1st instruction decoder 900, an instruction read request for a branch-desntination instruction is issued to an instruction cache 100. The instructions set in the BIRP 400 and BIRS 500 are stored in IFR 100, and the instruction set in the BIRP 400 is transferred to a selecting circuit 1010. Thus, two instructions are decoded in every machine cycle at the IF stage as a 1st instruction decoding stage and transferred to a D stage as a 2nd instruction decoding stage. At the 2nd instruction decoding stage, the instructions set in IRP 1200 and IRS 1300 are decoded by a 2nd instruction decoder 1700.

7. 发明专利

JP2001236223A INFORMATION PROCESSOR 失效
公开(公告)号：JP2001236223A
公开(公告)日：2001-08-31
申请号：JP2000044722
申请日：2000-02-22
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： HIRAOKA TORU , ITOI TOMONAGA , HAKAMATA MASASHI , TANAKA SHINICHI
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To improve a processing speed by advancing the decoding of a following instruction when address inter-lock is generated. SOLUTION: An address queue is arranged between an instruction decoding stage and an address adding stage. Thus, even when address interlock is generated, the decoding of the following instruction can be realized. When the instruction refers to a memory device, the decoded information of the instruction is stored in both the address queue and an instruction queue, and when the instruction does not refer to the memory device, the decoded information of the instruction is stored only in the instruction queue. Thus, when the instruction does not refer to the memory device, the execution of a pipe line stage necessary for referring to the memory device can be reduced, and the pipe line stage can be omitted. Therefore, it is possible for the following instruction to early refer to the memory device. As a result, it is possible to shield pipe line overhead due to the address interlock of the following instruction, and to improve the processing speed of the instruction.

8. 发明专利

JPH10301852A INFORMATION PROCESSOR 失效
公开(公告)号：JPH10301852A
公开(公告)日：1998-11-13
申请号：JP10857897
申请日：1997-04-25
申请人： HITACHI LTD , HITACHI CHIYOU LSI SYS KK
发明人： HIRAOKA TORU , ITOI TOMONAGA , HAKAMATA MASASHI , YOSHIHARA MAKOTO , KAWAMURA TOSHIAKI , KURIYAMA KAZUNORI
IPC分类号： G06F12/10
摘要： PROBLEM TO BE SOLVED: To shorten the processing time until obtaining segment table designation(STD) in large scale virtual address transformation(LVAT) by providing the transformation buffers of the two stages of a large scale virtual address segment table designation(LVSTD) and a large scale virtual address transformation buffer(LVLB) in a large scale virtual address transformation process. SOLUTION: One pair or plural LVSTD storage means 1000 store a part of a large scale virtual address(LVA) storage register 600 and the STD generated by an LVAT processing means 700 in a pair. The LVLB 1400 pairs a part of the LVA storage register 600 and the STD generated by the LVAT processing means 700 and stores a part of the LVA storage register 600 as a column address for plural. In such a manner, by providing the transformation buffers of the two stages of the LVSTD storage means 1000 and the LVLB 1400 in the large scale virtual address transformation process, the large scale virtual address transformation processing time is shortened.

9. 发明专利

JPH0991139A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0991139A
公开(公告)日：1997-04-04
申请号：JP25059795
申请日：1995-09-28
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , HITACHI INFORMATION TECHNOLOGY
发明人： NAKATANI AKIHIRO , ITOI TOMONAGA , INOUE TSUKASA
IPC分类号： G06F9/38
摘要： PROBLEM TO BE SOLVED: To increase pipe-line processing speed by selectively using either precedence operation or the preread of branching destination instruction at the time of the unused cycle of an instruction address adder. SOLUTION: When an instruction stored in an instruction register 4 for precedence instruction is an LR instruction, at an instruction address adder use method discrimination circuit 18, a value (such as a bit '1', for example) showing the preceding reading of the branching destination instruction is outputted to a line 18A but in the case of LA instruction, a value (such as a bit '0', for example) showing the precedence operation is outputted to a line 18 and applied to an adder input select signal generating circuit 17. Therefore, when the precedence instruction is the LR instruction and a following instruction is a BC instruction, the adder input select signal generating circuit 17 allows an instruction address adder 13 to execute branching destination instruction pre-reading function so that the processing of the BC instruction can be started earlier one cycle and an instruction 3 of a branching destination instruction example is put into the pipeline in the 7th cycle.

10. 发明专利

JPH07239781A INFORMATION PROCESSOR 失效
公开(公告)号：JPH07239781A
公开(公告)日：1995-09-12
申请号：JP5331594
申请日：1994-02-25
申请人： HITACHI LTD
发明人： ITOI TOMONAGA , KUROKAWA HIROSHI , YOSHINAGA TAKESHI
IPC分类号： G06F9/38
摘要： PURPOSE:To speed up the processing of a branch instruction by using a branch destination instruction which is already prefetched. CONSTITUTION:A buffer 218A is supposed to be a currently effective buffer. A nonconditional branch instruction is decoded and when the branch instruction is of a short-distance forward branching and the branch destination address is already prefetched in the buffer 218A, the output pointer 330A of the buffer is set to the branch destination address, and a conditional branch is decoded and when the decoded branch instruction is of the short-distance forward branching and the branch destination address is already prefetched in the buffer 218A, the data from the buffer 218A are selected by a selector 212A and stored in a buffer 220A. The buffer 220A is selected by a selector 226A and the output pointer 330A of the buffer is set to the branch destination address. Consequently, the branch destination instruction can be read out fast without sending an instruction request to a cache in any case.

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