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1. 发明专利

JP2005260350A Level shift circuit 有权
标题翻译：水平移位电路
公开(公告)号：JP2005260350A
公开(公告)日：2005-09-22
申请号：JP2004065903
申请日：2004-03-09
申请人： Hitachi Information Technology Co Ltd , 株式会社日立インフォメーションテクノロジー
发明人： KIYUNA TADASHI
IPC分类号： H03K19/0185
摘要： PROBLEM TO BE SOLVED: To provide a high-speed level shift circuit having low power consumption. SOLUTION: The circuit is provided with a first n-channel MOS transistor MN1 in which an input signal of a first power supply voltage level is inputted to a gate; a second n-channel MOS transistor MN2 in which a reverse input signal of the first power supply voltage level is inputted to a gate; third and fourth n-channel MOS transistors MN3, MN4 in which a second power supply potential is connected to each of their gates, and sources are connected to the drains of MN1, MN2; a first p-channel MOS transistor MP1 in which a second power supply voltage is used as a power supply, the gate is connected to the drain of MN2, and the drain is connected to the drain of MN3; and a second p-channel MOS transistor MP2 in which the gate is connected to the drain of MN1, and the drain is connected to the drain of MN4. Current driving performance of MP1, MN3 and MP2, MN4 in a non-saturation state are set the same, respectively. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供具有低功耗的高速电平移位电路。解决方案：电路设置有第一n沟道MOS晶体管MN1，其中第一电源电压电平的输入信号被输入到门; 第二n沟道MOS晶体管MN2，其中第一电源电压电平的反向输入信号被输入到栅极; 第三和第四n沟道MOS晶体管MN3，MN4，其中第二电源电位连接到它们的每个栅极，源极连接到MN1，MN2的漏极; 使用第二电源电压作为电源的第一p沟道MOS晶体管MP1，栅极连接到MN2的漏极，漏极连接到MN3的漏极; 以及第二p沟道MOS晶体管MP2，其中栅极连接到MN1的漏极，漏极连接到MN4的漏极。 MP1，MN3，MP2，MN4在非饱和状态下的电流驱动性能分别设定为相同。版权所有（C）2005，JPO＆NCIPI

2. 发明专利

JP2005006160A Programmable logic circuit and semiconductor integrated circuit 有权
标题翻译：可编程逻辑电路和半导体集成电路
公开(公告)号：JP2005006160A
公开(公告)日：2005-01-06
申请号：JP2003169103
申请日：2003-06-13
申请人： Hitachi Information Technology Co Ltd , Hitachi Ltd , 株式会社日立インフォメーションテクノロジー , 株式会社日立製作所
发明人： KIYUNA TADASHI , HOSHINO HISANOBU
IPC分类号： H01L21/82 , H03K19/173 , H03K19/177
摘要： PROBLEM TO BE SOLVED: To provide a technique for reducing the circuit scale of a programmable logic circuit.
SOLUTION: In this programmable logic circuit, there are arranged a plurality of multiply lines (102), a plurality of condition input signal lines (101) formed so as to intersect the multiply lines and switching circuits (100) provided at intersection places of the multiply lines and the condition input signal lines to determine a logic of a multiply line on the basis of a logic of a condition input signal line, corresponding to the multiply lines. There are further provided a plurality of memories (13 and 14) capable of storing information and an output logic (10) for obtaining a plurality of outputs corresponding to the multiply lines by performing a logical operation of the logic of the multiply lines and output signals of the memories, and the need for redundant multiply lines is eliminated to thereby reduce the circuit scale.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种减小可编程逻辑电路的电路规模的技术。解决方案：在该可编程逻辑电路中，布置有多条乘法线（102），多条条件输入信号线（101）形成为与交线相交，并且交叉电路乘法线的位置和条件输入信号线根据对应于乘法线的条件输入信号线的逻辑来确定乘法线的逻辑。还提供能够存储信息的多个存储器（13和14）和用于通过执行乘法线和输出信号的逻辑的逻辑运算来获得与乘法线相对应的多个输出的输出逻辑（10）的存储器，并且消除对冗余乘法线的需要，从而减小电路规模。版权所有（C）2005，JPO＆NCIPI

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