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1. 发明专利

JP2006013236A Method of manufacturing semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：JP2006013236A
公开(公告)日：2006-01-12
申请号：JP2004190062
申请日：2004-06-28
申请人： Hitachi High-Tech De Technology Co Ltd , Hitachi Hybrid Network Co Ltd , Renesas Technology Corp , 日立ハイテクデーイーテクノロジー株式会社 , 日立ハイブリッドネットワーク株式会社 , 株式会社ルネサステクノロジ
发明人： DEURA AKIRA , KIKUCHI SAKAE , SUDO KAZUO , FUJII NORIKAZU
IPC分类号： H01L23/12
CPC分类号： H01L24/97 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2924/15787 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve the connection reliability of a high-frequency semiconductor device incorporated in portable communication equipment, etc. SOLUTION: A substrate 9 of multiple allocation is prepared with a plurality of non-through holes 5c which are opened on the rear surface 5b of the substrate 9 and conductor sections 5d formed from the rear surface 5b to the non-through holes 5c. Then, after a semiconductor chip 1 is mounted on the device region of the substrate 9 and electrically connected to the substrate 9, a collective sealing section 10 is formed on the main surface 5a of the substrate 9 without allowing a silicone resin from entering into the non-through holes 5c by means of the bottoms 5e of the holes 5c by supplying the silicone resin onto the main surface 5a of the substrate 9. Consequently, the semiconductor device having the plurality of conductors 5d from the ends to the side faces of the rear surface 5b can be assembled, and the connection reliability of the semiconductor device can be improved. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提高结合在便携式通信设备中的高频半导体器件的连接可靠性等。解决方案：多个分配的基板9准备有多个非贯通孔5c 它们在基板9的后表面5b和从后表面5b到非通孔5c形成的导体部分5d之间打开。然后，在将半导体芯片1安装在基板9的器件区域上并电连接到基板9之后，在基板9的主表面5a上形成集合密封部分10，而不使硅树脂进入通过将硅树脂供给到基板9的主表面5a上，通过孔5c的底部5e形成非通孔5c。因此，具有从端部到端面的多个导体5d的半导体器件可以组装后表面5b，并且可以提高半导体器件的连接可靠性。版权所有（C）2006，JPO＆NCIPI

2. 发明专利

JP2005197400A Semiconductor module and manufacturing method therefor 审中-公开
标题翻译：半导体模块及其制造方法
公开(公告)号：JP2005197400A
公开(公告)日：2005-07-21
申请号：JP2004001001
申请日：2004-01-06
申请人： Hitachi Hybrid Network Co Ltd , Renesas Technology Corp , 日立ハイブリッドネットワーク株式会社 , 株式会社ルネサステクノロジ
发明人： ONO HIROSHI , KIKUCHI SAKAE , DEURA AKIRA , NISHI TAKAHIRO
IPC分类号： H01L25/18 , H01L25/04
CPC分类号： H01L24/32 , H01L2224/05554 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/49 , H01L2224/73265 , H01L2924/181 , H01L2924/19105 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To prevent dislocation of a semiconductor chip mounted on a semiconductor module without controlling the position of the semiconductor chip. SOLUTION: In the semiconductor module, the semiconductor chip is stored in a cavity formed in a substrate, and the semiconductor chip is fixed to a die pad at a bottom of the cavity. The die pad in the size of the mounted semiconductor chip is formed at the bottom of the cavity, where the semiconductor chip is stored. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了防止安装在半导体模块上的半导体芯片的位错，而不控制半导体芯片的位置。解决方案：在半导体模块中，将半导体芯片存储在形成在基板中的空腔中，并且将半导体芯片固定到空腔底部的管芯焊盘。所安装的半导体芯片的尺寸的芯片焊盘形成在空腔的底部，其中存储半导体芯片。版权所有（C）2005，JPO＆NCIPI

3. 发明专利

JP2005193935A Electronic component packing method and electronic component mounting method 审中-公开
标题翻译：电子元件封装方法和电子元件安装方法
公开(公告)号：JP2005193935A
公开(公告)日：2005-07-21
申请号：JP2004000868
申请日：2004-01-06
申请人： Hitachi Hybrid Network Co Ltd , Renesas Technology Corp , 日立ハイブリッドネットワーク株式会社 , 株式会社ルネサステクノロジ
发明人： SUDO KAZUO , KIKUCHI SAKAE , DEURA AKIRA , NISHI TAKAHIRO
IPC分类号： B65D73/02 , B65B15/04 , B65D85/86 , H05K13/02
摘要： PROBLEM TO BE SOLVED: To provide an electronic component packing method which enables packing an electronic component of directivity by a single specification. SOLUTION: In the electronic component packing method using a carrier tape in which an electronic component is stored in a cavity formed of a through hole in a base tape, and the cavity is covered by a cover tape affixed to the base tape, a peelable cover tape is affixed to one side of the base tape, the electronic component is stored in the cavity formed by the affixed cover tape and the through hole in the base tape, a peelable cover tape is affixed to the other side of the base tape. In the mounting, the electronic component is stored in the cavity, the direction of the carrier tape is changed according to the electronic component mounting method, and the electronic component stored in the carrier tape is taken out and mounted while peeling either cover tape located on the top side. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够通过单一规格包装方向性的电子部件的电子部件包装方法。解决方案：在使用其中电子部件存储在由基带中的通孔形成的空腔中的载带的电子部件填充方法中，并且空腔被固定在基带上的盖带覆盖，将可剥离的盖带固定在基带的一侧上，电子部件被存储在由固定的盖带和基带中的通孔形成的空腔中，可剥离的盖带被固定到基座的另一侧胶带。在安装中，将电子部件存储在空腔中，根据电子部件安装方法改变载带的方向，并且将剥离存放在载带上的电子部件取出并安装，同时剥离位于顶端。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2007074001A Semiconductor device 审中-公开
公开(公告)号：JP2007074001A
公开(公告)日：2007-03-22
申请号：JP2006339318
申请日：2006-12-18
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： KAMISHIRO IWAMICHI , KIKUCHI SAKAE , NUNOKAWA YASUHIRO , KONDO SHIZUO , ADACHI TETSUAKI
IPC分类号： H01L21/60
CPC分类号： H01L24/05 , H01L24/06 , H01L2224/04042 , H01L2224/05 , H01L2224/05554 , H01L2224/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/49 , H01L2224/49175 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/1306 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can be miniaturized. SOLUTION: In the semiconductor device, a semiconductor chip 5 in which a plurality of amplification means are formed is mounted at one main surface of a wiring board 1, and the electrode of the semiconductor chip is electrically connected to that of the wiring board with a wire. In the semiconductor device, an electrode 2C for bonding at a substrate side to which a wire 7C fixed to reference potential is connected, is arranged at a position far remote from one side 5X of the semiconductor chip 5, as compared with an electrode 2B for outputting at the substrate side to which a wire 7B for outputting is connected. An electrode 2A for inputting at the substrate side to which a wire 7A for inputting is connected, is arranged at a position where distance from one side 5X of the semiconductor chip 5 becomes nearly identical to that of the electrode 2B for outputting at the substrate side, or at a position far remote from one side 5X of the semiconductor chip 5 as compared with the electrode 2C for bonding at the substrate side. COPYRIGHT: (C)2007,JPO&INPIT

5. 发明专利

JP2010016396A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010016396A
公开(公告)日：2010-01-21
申请号：JP2009205653
申请日：2009-09-07
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： KAMISHIRO IWAMICHI , KIKUCHI SAKAE , NUNOKAWA YASUHIRO , KONDO SHIZUO , ADACHI TETSUAKI
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L2224/05553 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/49 , H01L2224/49113 , H01L2224/49175 , H01L2224/49433 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/1306 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device aiming at miniaturization while suppressing deterioration of high frequency characteristics. SOLUTION: A semiconductor chip 5 mounted on the main surface of a wiring board 1 includes a chip side input electrode 6A electrically connected to the input part of a first amplifying means PW1, and a chip side output electrode 6B electrically connected to the output part of a second amplifying means PW2, the wiring board 1 has a board side input electrode 2A and a board side output electrode 2B on the main surface, the output part of the first amplifying means PW1 is electrically connected to the input part of the second amplifying means PW2, the chip side input electrode 6A is electrically connected to the board side input electrode 2A by an input wire 7A, the chip side input electrode 6B is electrically connected to the board side output electrode 2B by an output wire 7B, the input wire 7A is formed so as to straddle one side of a pair of the first sides forming the flat shape of the semiconductor chip 5, and the output wire 7B is formed so as to straddle one side of a pair of second sides. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种旨在小型化的半导体器件，同时抑制高频特性的劣化。解决方案：安装在布线板1的主表面上的半导体芯片5包括：电连接到第一放大装置PW1的输入部分的芯片侧输入电极6A和电连接到第一放大装置PW1的芯片侧输出电极6B 第二放大装置PW2的输出部分，布线板1在主表面上具有板侧输入电极2A和基板侧输出电极2B，第一放大装置PW1的输出部分电连接到第二放大装置PW2，芯片侧输入电极6A通过输入导线7A电连接到基板侧输入电极2A，芯片侧输入电极6B通过输出导线7B与板侧输出电极2B电连接，输入线7A形成为跨越形成半导体芯片5的平坦形状的一对第一侧的一侧，并且输出线7B形成为跨越一对线的一侧 cond侧。版权所有（C）2010，JPO＆INPIT

6. 发明专利

JP2007074000A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2007074000A
公开(公告)日：2007-03-22
申请号：JP2006339316
申请日：2006-12-18
申请人： Renesas Eastern Japan Semiconductor Inc , Renesas Technology Corp , 株式会社ルネサステクノロジ , 株式会社ルネサス東日本セミコンダクタ
发明人： KAMISHIRO IWAMICHI , KIKUCHI SAKAE , NUNOKAWA YASUHIRO , KONDO SHIZUO , ADACHI TETSUAKI
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L24/05 , H01L2224/04042 , H01L2224/05554 , H01L2224/05599 , H01L2224/48 , H01L2224/48091 , H01L2224/48227 , H01L2224/484 , H01L2224/49 , H01L2224/49175 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/1306 , H01L2924/13091 , H01L2924/15153 , H01L2924/1517 , H01L2924/19105 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can be miniaturized. SOLUTION: In the semiconductor device, a semiconductor chip 5 in which a plurality of amplification means are formed is mounted at one main surface of a wiring board 1, and the electrode of the semiconductor chip is electrically connected to that of the wiring board with a wire. In the semiconductor device, an electrode 2C for bonding at a substrate side to which a wire 7C fixed to reference potential is connected, is arranged at a position far remote from one side 5X of the semiconductor chip 5, as compared with an electrode 2B for outputting at the substrate side to which a wire 7B for outputting is connected. An electrode 2A for inputting at the substrate side to which a wire 7A for inputting is connected, is arranged at a position where distance from one side 5X of the semiconductor chip 5 becomes nearly identical to that of the electrode 2B for outputting at the substrate side, or at a position far remote from one side 5X of the semiconductor chip 5 as compared with the electrode 2C for bonding at the substrate side. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供可以小型化的半导体器件。解决方案：在半导体器件中，其中形成有多个放大装置的半导体芯片5安装在布线板1的一个主表面上，半导体芯片的电极与布线的电极电连接用电线板。在半导体装置中，与用于固定参考电位的导线7C连接的基板侧的用于接合的电极2C被布置在远离半导体芯片5的一侧5X的位置，与用于在连接用于输出的导线7B的基板侧输出。用于在基板侧输入用于输入用导线7A的基板侧的电极2A配置在距离半导体芯片5的一侧5X的距离与用于在基板侧输出的电极2B的距离几乎相同的位置，或者与用于在基板侧接合的电极2C相比，远离半导体芯片5的一侧5X的位置。版权所有（C）2007，JPO＆INPIT

7. 发明专利

JP2007088363A Electronic equipment 审中-公开
标题翻译：电子设备
公开(公告)号：JP2007088363A
公开(公告)日：2007-04-05
申请号：JP2005277960
申请日：2005-09-26
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： DEURA AKIRA , ONO IKUYUKI , KOZU TADASHI , TANIMOTO TAKUMA , KAMISHIRO IWAMICHI , KIKUCHI SAKAE , MORIYAMA SHINJI
IPC分类号： H01F27/06 , H01L23/12
CPC分类号： H01L2224/32225 , H01L2224/45015 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/00011 , H01L2924/1305 , H01L2924/13091 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/207 , H01L2924/01033
摘要： PROBLEM TO BE SOLVED: To improve the performance of a power amplification module by reducing the influence exerted by magnetic flux generated with an air coil on interconnect lines of the interior or the front surface of a wiring board. SOLUTION: The RF power module 1 as an electronic equipment mounts semiconductor chips, passive components, and an air coil 6 on a wiring board 3; and seals them with sealant resin. The RF power module 1 has two systems of a power amplification circuit, and each of the power amplification circuit is configured so as to be possible to amplify signals of multiple bands. The air coil 6 is used in an output matching circuit. The air coil 6 of surface mount type comprises a coil 6a which coils a conductor wire 31 more than once, and two terminals 6b composed of the conductor wire 31 connected respectively to the both ends of the coil 6a. The conductor wire 31 comprising the coil 6a is covered by an insulating film, and the conductor wire 31 comprising the each terminals 6b with the insulating film removed therein is connected through a solder 32 to the board side terminal 12a which is in a position distant from the coil 6a, extending therethrough in the direction apart from the coil 6a. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过减少由空气线圈产生的磁通量对布线板的内部或前表面的布线的影响而提高功率放大模块的性能。解决方案：作为电子设备的RF功率模块1将半导体芯片，无源部件和空气线圈6安装在布线板3上; 并用密封胶密封。 RF功率模块1具有功率放大电路的两个系统，并且每个功率放大电路被配置为可以放大多个频带的信号。空气线圈6用于输出匹配电路。表面安装型的空气线圈6包括一个线圈6a，其不止一次地缠绕导体线31，以及两个由分别连接到线圈6a两端的导线31构成的端子6b。包括线圈6a的导线31被绝缘膜覆盖，并且包括其中去除了绝缘膜的每个端子6b的导体线31通过焊料32连接到位于远离的位置的板侧端子12a 线圈6a沿着与线圈6a分离的方向延伸穿过。版权所有（C）2007，JPO＆INPIT

8. 发明专利

JP2007220790A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2007220790A
公开(公告)日：2007-08-30
申请号：JP2006037931
申请日：2006-02-15
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： SASAKI KENJI , TAGAMI TOMONORI , KIKUCHI SAKAE , MAKINO TOSHIBUMI , SATO TAKESHI , KOBORI TSUTOMU , UMEMOTO YASUNARI , KITAHARA TAKASHI
IPC分类号： H01L25/18 , H01L21/331 , H01L25/04 , H01L29/737 , H01L29/78
CPC分类号： H04B1/28 , H01L23/66 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/78 , H01L24/85 , H01L25/18 , H01L2223/6644 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/49113 , H01L2224/49171 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/92247 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01031 , H01L2924/01033 , H01L2924/01049 , H01L2924/01074 , H01L2924/01079 , H01L2924/10329 , H01L2924/10336 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a technology to reduce the size of an RF module to be used for a mobile phone, etc. SOLUTION: On a wiring board 26 which constitutes the RF module 25, a semiconductor chip 28 formed with an amplifier circuit and a semiconductor chip 27 formed with a control circuit for controlling the amplifier circuit are mounted. Bonding pads 30 on the semiconductor chip 27 and bonding pads 31 on the semiconductor chip 28 are directly connected with a wire 32, not via relay pads. The shape of the bonding pads 31 formed on the semiconductor chip 28 is not square but rectangular (oblong). COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：解决方案：提供一种降低用于移动电话的RF模块的尺寸的技术等。解决方案：在构成RF模块25的布线板26上，具有半导体芯片 28形成有放大器电路和形成有用于控制放大器电路的控制电路的半导体芯片27。半导体芯片27上的接合焊盘30和半导体芯片28上的焊盘31直接与导线32连接，而不是通过中继焊盘。形成在半导体芯片28上的接合焊盘31的形状不是正方形，而是矩形（长方形）。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2007088123A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007088123A
公开(公告)日：2007-04-05
申请号：JP2005273242
申请日：2005-09-21
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： ARAI REIICHI , ITO MAMORU , KIKUCHI SAKAE , NIITSU TOSHIJI
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To inhibit the generation of a void during soldering in the case of the mounting of an electronic loaded article by changing the pattern of a solder mask.
SOLUTION: The solder mask 30 is composed of mask patterns 31 used for supplying solder for mounting a ground terminal at the center, and the mask patterns 32 used for supplying the solder for mounting a signal terminal at the peripheries of the mask patterns 31. Non-openings 33 formed among openings 31a, 31b, 31c and 31d constituting the mask patterns 31 are formed in a folding fan shape, so that the widths (b) on the peripheral side are wider than those (a) of the central side. When a mounting is conducted by using such a solder mask 30 having such a constitution, the generation of the large voids can also be inhibited in the case of a reflow solder and the number of the generation of void themselves.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：通过改变焊接掩模的图案来防止在电子负载制品的安装的情况下在焊接期间产生空隙。解决方案：焊接掩模30由用于提供用于在中心安装接地端子的焊料的掩模图案31和用于在掩模图案的周边处提供用于安装信号端子的焊料的掩模图案32 形成在构成掩模图案31的开口31a，31b，31c和31d之间的非开口33形成为折叠扇形，使得周边侧的宽度（b）比中央（a）的（a）宽侧。当通过使用具有这种结构的这种焊接掩模30进行安装时，在回流焊料的情况下以及空隙本身的数量也可以抑制大的空隙的产生。版权所有（C）2007，JPO＆INPIT

10. 发明专利

JP2007088220A Manufacturing method of semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007088220A
公开(公告)日：2007-04-05
申请号：JP2005275389
申请日：2005-09-22
申请人： Renesas Technology Corp , 株式会社ルネサステクノロジ
发明人： NISHI TAKAHIRO , SUDO KAZUO , SATO TAKESHI , DEURA AKIRA , KAMISHIRO IWAMICHI , ONO HIROSHI , KIKUCHI SAKAE , NIITSU TOSHIJI , ITO MAMORU
IPC分类号： H01L21/60
CPC分类号： H01L24/73 , H01L2224/0401 , H01L2224/05624 , H01L2224/13099 , H01L2224/16 , H01L2224/32225 , H01L2224/45 , H01L2224/45144 , H01L2224/48 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48465 , H01L2224/48471 , H01L2224/48475 , H01L2224/48624 , H01L2224/48992 , H01L2224/48997 , H01L2224/73265 , H01L2224/78 , H01L2224/78301 , H01L2224/7855 , H01L2224/85 , H01L2224/85051 , H01L2224/85148 , H01L2224/85181 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85947 , H01L2224/85951 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/13091 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15787 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19105 , H01L2924/30105 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/48455
摘要： PROBLEM TO BE SOLVED: To improve the connection reliability of a semiconductor chip using wire bonding technology.
SOLUTION: A ball bonding operation 21a is carried out as a first connection 21 using a ball formed on the tip of a capillary at the side of a semiconductor chip 15a. A thermocompression bonding operation 22a that crushes and fixes the wire by pressure with the tip of the capillary is carried out as a second connection 22 at the side of a semiconductor chip 15b. Thereafter, a ball is formed on the tip of the capillary at the side of the second connection 22, and a ball bonding operation 22b is carried. As mentioned above, the ball bonding operation 22b is carried out last, whereby the thermocompression bonding 22a is improved in strength.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：使用引线接合技术提高半导体芯片的连接可靠性。解决方案：使用形成在半导体芯片15a侧的毛细管尖端上的球作为第一连接21进行球接合操作21a。作为在半导体芯片15b一侧的第二连接22，进行利用毛细管的顶端压力而将电线破碎并固定的热压接操作22a。此后，在第二连接22侧的毛细管的尖端上形成球，并且承载球接合操作22b。如上所述，最后进行球接合操作22b，从而提高热压接22a的强度。版权所有（C）2007，JPO＆INPIT

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