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1. 发明专利

JPS57127885A Backup device for pressure of air for instrumentation 失效
标题翻译：用于仪器空气压力的备用装置
公开(公告)号：JPS57127885A
公开(公告)日：1982-08-09
申请号：JP1303181
申请日：1981-02-02
申请人： Hitachi Ltd , Hitachi Eng Co Ltd
发明人： MIZUNO HIROYUKI , SONODA MASANOBU
IPC分类号： G21D1/00 , G21C17/00
CPC分类号： Y02E30/40

2. 发明专利

JPS5762389A Steam condensation device 失效
标题翻译：蒸汽冷凝装置
公开(公告)号：JPS5762389A
公开(公告)日：1982-04-15
申请号：JP13585380
申请日：1980-10-01
申请人： Hitachi Eng Co Ltd , Hitachi Ltd
发明人： MIZUNO HIROYUKI , SONODA MASANOBU
IPC分类号： F22B37/50 , F22B37/48 , F28B3/04 , G21D1/02 , G21D5/06
CPC分类号： Y02E30/40
摘要： PURPOSE: To provide an effective cooling and highly efficient recovery of a drain of high temperature and high pressure from a steam load by a method wherein a pure water is injected into a pipe for use in transporting drain of high temperature and high pressure after the steam load in the BWR nuclear power plant and then the drain is cooled to be condensed.
CONSTITUTION: Pure water in the pure water tank 9 is injected from the injector device A through a pressure increasing pump 14, a flow rate control valve 15 and a pure water supplying pipe 10 into a piping 3 for transporting the drain of high temperature and high pressure out of the stem load. Then, the drain of high temperature and high pressure is mixed with pure water and cooled to be condensed, and finally recovered into the drain recovery tank 7. In this way, it is possible to provide a highly efficient recovery of drain of high temperature and high pressure.
COPYRIGHT: (C)1982,JPO&Japio
摘要翻译：目的：通过以下方法提供高温和高压排水的有效冷却和高效回收，其中将纯水注入用于输送高温高压蒸汽的管道中，蒸汽在BWR核电站中负载，然后冷却冷凝水。构成：纯水槽9中的纯水通过增压泵14，流量控制阀15和纯水供给管10从注射装置A注入到用于输送高温高压力超出阀杆负荷。然后，将高温高压排水与纯水混合并冷却冷凝，最后回收到排水回收罐7中。这样可以高效地回收高温排水，高压力。

3. 发明专利

JPS57144499A NUCLEAR REACTOR WASTE HEAT RECOVERING DEVICE 失效
公开(公告)号：JPS57144499A
公开(公告)日：1982-09-07
申请号：JP2984981
申请日：1981-03-04
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： SONODA MASANOBU , SHIRAISHI TADASHI , MIZUNO HIROYUKI , SEKINE YASUHIRO
IPC分类号： G21D5/06 , G21D9/00

4. 发明专利

JP2007259463A Low power processor 有权
标题翻译：低功率处理器
公开(公告)号：JP2007259463A
公开(公告)日：2007-10-04
申请号：JP2007101243
申请日：2007-04-09
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： TOTSUKA YONETARO , ISHIBASHI KOICHIRO , MIZUNO HIROYUKI , NISHII OSAMU , UCHIYAMA KUNIO , SHIMURA TAKANORI , SEKINE ASAKO , KATSUKI YOICHI , NARITA SUSUMU
IPC分类号： H03K19/00 , G06F15/78 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/094
CPC分类号： Y02D10/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit managing both a high speed and low power consumption. SOLUTION: The low power processor has a logic circuit 902 and a substrate bias control circuit 903. The logic circuit is controlled so as not to change inputs of the logic circuit after switched to a low power mode in response to the execution of an instruction. After the circuit is switched to a high-speed mode in response to an interruption, the circuit starts operation after a substrate bias voltage applied to an MOS transistor of the logic circuit has been stabilized to a predetermined level. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种管理高速度和低功耗的半导体集成电路。解决方案：低功率处理器具有逻辑电路902和衬底偏置控制电路903.逻辑电路被控制为在响应于执行方式切换到低功率模式后不改变逻辑电路的输入一个指令在电路响应于中断而切换到高速模式之后，在施加到逻辑电路的MOS晶体管的衬底偏置电压已经稳定到预定电平之后，电路开始工作。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2000357962A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2000357962A
公开(公告)日：2000-12-26
申请号：JP25531799
申请日：1999-09-09
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI , ISHIBASHI KOICHIRO , NARITA SUSUMU
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/00 , H03K19/094
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor circuit device with which saves power consumption. SOLUTION: This device is provided with a first circuit to be controlled 100, consisting of at least one MOS transistor and a substrate bias control means 102 for generating substrate bias potential of the MOS transistor and is the one of permitting a comparatively large current to flow between the drain and the source of the MOS transistor, by arranging the means 102 to be a first state and for controlling a comparatively large current to be a smaller value between the drain and the source of the MOS transistor by arranging the means 102 to be a second state. In this case, the device is controlled in such a way that value of a substrate bias to be given to the first circuit to be controlled in the second state is a voltage value which is higher than that in the first state, concerning the substrate bias of a PMOS transistor and is the voltage value which is lower for the substrate bias of an NMOS transistor and that a power source voltage to be given to the first circuit to be controlled in the second state becomes smaller than that in the first state.

6. 发明专利

JP2000293983A DATA PROCESSING SYSTEM 失效
公开(公告)号：JP2000293983A
公开(公告)日：2000-10-20
申请号：JP10211999
申请日：1999-04-09
申请人： HITACHI LTD
发明人： SUGANO YUSUKE , MIZUNO HIROYUKI , WATABE TAKAO , MIURA SEISHI , AYUKAWA KAZUSHIGE
IPC分类号： G06F12/08 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To increase access speed for a memory in a data processing system. SOLUTION: Discriminating means 103, 203 of TAG are provided respectively in a memory controller 113 and a memory 200 having a cache holding mechanism. The cache holding mechanism of a memory is mechanism having a temporary storage section 21 which can hold one part of stored information of a memory cell array as a sub-set with a memory cell array 20. The discriminating means discriminates whether an access address required by a processor is hit to an address of information existing in the temporary storage section or not. Speed of information to a processor responding to a discriminated result and access operation used for a cache holding mechanism in the memory 200 can be increased by performing hit discrimination of the cache holding mechanism by both of the memory controller 113 and the memory 200.

7. 发明专利

JP2000078004A Semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路设备
公开(公告)号：JP2000078004A
公开(公告)日：2000-03-14
申请号：JP24930598
申请日：1998-09-03
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： MIZUNO HIROYUKI , AOKI HIROKAZU , ISHIBASHI KOICHIRO
IPC分类号： G06F1/10 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide an oscillation circuit supplying the clock of low skew/low jitter and in addition a high speed semiconductor integrated circuit by means of it in the logic circuit and the memory circuit of a micro processor and the like. SOLUTION: A first ring oscillation circuit (OSC11) where plural inventors 110 are connected in a ring form, a second ring oscillation circuit (OSC12) where plural inventors are connected in the ring form a and a conductive wiring are installed. The output of at least one inverter in the first ring oscillation circuit and the output of at least one inverter in the second ring oscillation circuit are connected to the conductive wiring. A switch circuit (SW1112) is arranged in the conductive wiring connecting the output of the first ring oscillation circuit and the output of the second ring oscillation circuit.
摘要翻译：要解决的问题：提供一种提供低偏移/低抖动时钟的振荡电路以及另外通过微处理器等的逻辑电路和存储电路中的高速半导体集成电路。解决方案：安装多个发明人110的环形振荡电路（OSC11），多个发明者以环形式连接的第二环形振荡电路（OSC12）和导电布线。第一环形振荡电路中的至少一个逆变器的输出和第二环形振荡电路中的至少一个反相器的输出连接到导电布线。在连接第一环形振荡电路的输出和第二环形振荡电路的输出的导体布线中布置开关电路（SW1112）。

8. 发明专利

JPH10289043A SEMICONDUCTOR DEVICE AND INFORMATION PROCESSOR 失效
公开(公告)号：JPH10289043A
公开(公告)日：1998-10-27
申请号：JP9560897
申请日：1997-04-14
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI
IPC分类号： G06F3/00 , G06F13/36
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which attempts low power consumption even though it can be used together with a standard product. SOLUTION: This semiconductor device is provided with at least one processor CPU1, a bus A 200, at least one 1st device DRAM1 which is connected to the processor CPU1 through the bus A 200, a bus B 201 whose signal amplitude is larger than the signal amplitude of the bus A 200 and a bus bridge 100 which is connected to the processor CPU1 through the bus A 200 and is also connected to the bus B 201. The bridge 100 converts the amplitude level of a signal on the bus A 200 and transfers it to the bus B 201, and converts the amplitude level of a signal on the bus B 201 and transfers it to the bus A 200.

9. 发明专利

JPH10260896A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10260896A
公开(公告)日：1998-09-29
申请号：JP6591697
申请日：1997-03-19
申请人： HITACHI LTD
发明人： WATABE TAKAO , TONOMURA MOTONOBU , MIKI YOSHIO , MIZUNO HIROYUKI , ITO KIYOO
IPC分类号： G06F12/04 , G06F12/08 , G11C11/401
摘要： PROBLEM TO BE SOLVED: To make a semiconductor device possible to deal with larger program without increasing the chip area, by converting data in a chip, storing compressed data in a memory, extending it at the time of loading it in a cache memory and using it by a processor. SOLUTION: An encoder ENC compresses data and the data are stored in a memory DRAM. A decoder DEC extends data and loads them on the cache memory CACHE. Even if some overhead is generated in the access time of the memory DRAM by the processing of the decoder DEC and the encoder ENC, it hardly affects the information processing ability of the processor CPU. Thus, larger program can be dealt in the processor CPU incorporating the memory DRAM without adversely affecting information processing ability.

10. 发明专利

JPH10242839A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH10242839A
公开(公告)日：1998-09-11
申请号：JP4523597
申请日：1997-02-28
申请人： HITACHI LTD
发明人： ITO KIYOO , MIZUNO HIROYUKI
IPC分类号： G05F3/20 , G11C5/14 , G11C11/407 , G11C11/408 , H01L21/8238 , H01L27/092 , H02M3/07 , H03K17/08 , H03K17/22 , H03K19/00 , H03K19/003 , H03K19/0948
摘要： PROBLEM TO BE SOLVED: To obtain a stable, high-speed CMOS circuit with small power consumption by controlling the well voltage of the CMOS circuit at the time of a power-ON operation, a normal operation, and a power-OFF operation. SOLUTION: When the power source is turned ON, a circuit block CT 2 selects voltages which are high enough to cut off transistors, i.e., 3.3V for a PMOS FET and -1.5V for an NMOSFET. Then a low voltage VCC2 is applied. The threshold voltage VT of the transistor is sufficiently high, so subthreshold currents are not accumulated to generate an excessive chip current, so no latch-up phenomenon is caused. In the normal operation, the voltage of substrates NW and PW are made shallow (2.3V and -0.5V) and the threshold voltage VT is made low for the operation, thereby reducing the power consumption. When the power source is turned OFF, the substrate voltages are made sufficiently high, the VCC2 is turned OFF, and then the source voltage VCC1 is turned OFF. When the source voltages are applied, the high source voltage VCC1 is applied and then the low source voltage VCC2 is inputted.

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