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1. 发明专利

JPS60190020A Cmos integrated circuit device 失效
标题翻译： CMOS集成电路设备
公开(公告)号：JPS60190020A
公开(公告)日：1985-09-27
申请号：JP4547184
申请日：1984-03-12
申请人： Hitachi Control Syst Co Ltd , Hitachi Ltd
发明人： KODAMA KAZUYUKI , KITATSUME YOSHIAKI , AKIYAMA MASAKAZU , ISHIKAWA KATSUFUMI , OONUMA KUNIHIKO
IPC分类号： H03K19/0948 , G01R31/28 , G06F1/04 , G10L11/00 , G10L15/28 , H03K17/16
CPC分类号： H03K17/16
摘要： PURPOSE:To decrease a peak value of a power noise produced at signal switching without incurring the increase in a chip area by retarding a switching timing of plural output signals by a prescribed time at each several signal line bundles. CONSTITUTION:In case of, e.g., a voice recognition CMOSLSI circuit, 20 data lines D are divided into D1 in 6-bit and D2, D3 in 7-bit, the D1 is latched to a memory address register MAR1 in the timing of CK, the D2 is latched to an MAR2 by using a clock CK2 delayed by a delay time of the two stages of inverters INV than the time of the CK, and the D3 is latched in an MAR3 by using a clock CK3 delayed by the delay time of two stages of the INV than the time of the CK2. Thus, six lines are switched in the timing of the CK, seven lines are switched in the timing of the CK2 and seven lines are switched sequentially in the timing of the CK3 in the output circuit. Thus, the peak current produced in the output circuit and power supply is decreased at the switching of data in 20-bit.
摘要翻译：目的：降低在信号切换时产生的功率噪声的峰值，而不会在每个几个信号线束处延迟多个输出信号的开关定时预定时间，而不会导致芯片面积的增加。规定：在例如语音识别CMOSLSI电路的情况下，20条数据线D被分成6位的D1和D2，7位的D3，在CK的定时中将D1锁存到存储器地址寄存器MAR1 通过使用延迟了两级反相器INV的延迟时间的时钟CK2比CK的时间将D2锁存到MAR2，并且通过使用延迟延迟时间的时钟CK3将D3锁存在MAR3中的两个阶段的INV比CK2的时间。因此，在CK的定时中切换六条线，在CK2的定时切换七条线，并且在输出电路中的CK3的定时中顺序切换七条线。因此，在20位的数据切换时，输出电路和电源产生的峰值电流降低。

2. 发明专利

JPS58137164A MAGNETIC STORAGE DEVICE 失效
公开(公告)号：JPS58137164A
公开(公告)日：1983-08-15
申请号：JP1756182
申请日：1982-02-08
申请人： HITACHI LTD
发明人： SUZUKI KUNIO , OONUMA KUNIHIKO
IPC分类号： G11B19/00 , G11B19/04
摘要： PURPOSE:To solve the start-stop problems of a storage device easily, by providing the storage device side with a signal which is set in power recovery and reset when a mechanism is held in readiness or on OR conditions after the power recovery processing time of the mechanism. CONSTITUTION:Durting date reading operation, read data 13 from a driving device (mechanism) 10 is stored in a data buffer memory 7 via a control circuit 9 and then sent to a channel 2. Information showing an error of the mechanism 10 is set in a status register 8 via the control circuit and also sent to the channel 2. A power recovery detector 17, on the other hand, detects the starting of an AC power source to output a pulse and then sets an FF20 and also starts a timer 18; when its output 8-1 or the ready signal 16 of the mechanism 10 goes up to 1, the output of the FF20 is passed through an OR gate 19 and inputted to the channel 2 through the register 8. A computer decides on the bits of the register 8 to decide on whether a not-ready signal originates from the power recovery processing or not, performing necessary processing.

3. 发明专利

JPS5880757A DATA TRANSFER CONTROLLING METHOD 失效
公开(公告)号：JPS5880757A
公开(公告)日：1983-05-14
申请号：JP17724681
申请日：1981-11-06
申请人： HITACHI LTD
发明人： SUZUKI KUNIO , OONUMA KUNIHIKO , NAKAMURA KUNIO
IPC分类号： G06F13/00 , G06F13/12 , G06F15/16 , G06F15/177
摘要： PURPOSE:To ensure the averaged transfer of data between each computer and an input/output device, by stopping temporarily the transmission of the start signal from a channel through a controller and meanwhile processing the start signal given from another channel in case an error recovering process is neeeded. CONSTITUTION:The channels CH0-CH2 are set in accordance with computers CPU0-CPU2 respectively. In case the start signal is given to a controller CE from either one of the channels CH0-CH2 via a switching device SW, the controller CE receives the control signal related to the transfer of data from a computer corresponding to the relevant channel and then performs the transfer of data. In this case, if an error which can be recovered arises at a data transfer control input/output device and an error recovering process is needed, the controller CE stops temporarily the start signal which is given from either one of the channels. Meanwhile the start signal given from another channel is scanned, and the transfer of data is controlled.

4. 发明专利

JPS56153824A DIGITAL FILTER 失效
公开(公告)号：JPS56153824A
公开(公告)日：1981-11-28
申请号：JP12974980
申请日：1980-09-17
申请人： HITACHI LTD
发明人： OONUMA KUNIHIKO , HIRAI KOUJI , IDE TOSHIYUKI
IPC分类号： H03H17/02
摘要： PURPOSE:To obtain an inexpensive digital filter which is capable of a multi-spot input, by making use of a large-capacity shift register. CONSTITUTION:A digital filter is formed with the following devices: a large-capacity and multi-bit dynamic shift register 1 that stores all interruption information given from the circuit 11; a multiplexer 2 which gives a time division to the interruption input; an AND gate 3; an OR gates 4; a 4-bit shift register 5; an FF6 which store the most significant bit of register 5; an exclusive OR gate 7; a 4-notation counter 8; a counter 9; a clock generator 10; an AND gate 15; an inverter 16; AND gates 17 and 18; an OR gate 19; and an FF20 that stores temporarily the state of the selected circuit. In such consistion, an inexpensive digital filter capable of a multi- spot input is obtained.

5. 发明专利

JPS5352988A PREVENTING DEVICE OF CONNECTOR DROP 失效
公开(公告)号：JPS5352988A
公开(公告)日：1978-05-13
申请号：JP12719676
申请日：1976-10-25
申请人： HITACHI LTD
发明人： NISHIDA TAKEHIKO , OONUMA KUNIHIKO
IPC分类号： H01R13/639
摘要： PURPOSE:To form to enable to maintain surely combined state in the both connectors, by preparing a suitable engaged parton both connectors, and enabling the preventing cover to be dropped to touch and detach simply.

6. 发明专利

JPS6044695B2 JPS6044695B2 - 失效
公开(公告)号：JPS6044695B2
公开(公告)日：1985-10-04
申请号：JP9696877
申请日：1977-08-15
申请人： Hitachi Ltd
发明人： NISHIDA TAKEHIKO , OONUMA KUNIHIKO
IPC分类号： G06F7/00 , G06F5/00 , G06F5/01 , G06F7/76

7. 发明专利

JPS6077250A CONTROLLING METHOD OF DISC CACHE MEMORY 失效
公开(公告)号：JPS6077250A
公开(公告)日：1985-05-01
申请号：JP18506883
申请日：1983-10-05
申请人： HITACHI LTD
发明人： TANJI MASAYUKI , OONUMA KUNIHIKO
IPC分类号： G06F12/08
摘要： PURPOSE:To attain loading/unloading of a memory board in holding the function by constituting a memory interface of a disc cache device like a structure enabled to load/unload an active line and informing the memory board to be loaded/unloaded to a control device. CONSTITUTION:In normal operating status, cache memories 500-800 are filled with data. When a maintenance command is executed from a console 400 to unload a memory board, a microprocessor in a control device 300 sets up flags for access inhibition and data invalidation to two corresponding directories. Conseqently, the block is made unrelated to caching operation and the memory board including the block can be unloaded. If a memory board is to be loaded, the access inhibition flag is reset by the similar procedure. Although the data in the loaded memory board are invalid immediately after the loading, the written data are made valid and then the status before the loading/unloading is gradually restored.

8. 发明专利

JPS6055792A DYNAMIC CONVERGENCE DEVICE 失效
公开(公告)号：JPS6055792A
公开(公告)日：1985-04-01
申请号：JP16315983
申请日：1983-09-07
申请人： HITACHI LTD
发明人： TOMITA KIKUO , OONUMA KUNIHIKO
IPC分类号： H04N9/28 , H04N9/29 , H04N17/04
摘要： PURPOSE:To set the color blurring correction data in accordance with an optional area with a simple external operation by adding a memory to store the color blurring correction data for each area. CONSTITUTION:A memory 66 storing the color blurring correction data for each area is used in addition to a correction data memory 62 storing the reference color blurring correction data. The correction data 1-n stored in the memory 66 are selected optionally by an external switch 67. The correction data read out of the memory 62 is added 65 to the correction data selected by the switch 67 and supplied to a color blurring correction coil 3 via a D/A converter 63. Thus the color blurring correction data can be set in accordance with an optional area with a simple external operation.

9. 发明专利

JPS5963015A Rotable body magnetic memory device 失效
标题翻译：可旋转的身体磁性记忆装置
公开(公告)号：JPS5963015A
公开(公告)日：1984-04-10
申请号：JP17318682
申请日：1982-10-04
申请人： Hitachi Ltd
发明人： TANJI MASAYUKI , NAKAMURA KUNIO , OONUMA KUNIHIKO
IPC分类号： G06F3/06 , G11B20/18
CPC分类号： G11B20/1816
摘要： PURPOSE:To execute self-prevention and preservation of a data without the burden of a software and a drop of the throughput, and also to suppress a drop of the processing property by writing automatically a correct data after correction in a part where an error is generated, in case when a read error is detected and it is corrected. CONSTITUTION:A flip-flop circuit by gates 530-570 and NOR gates 260, 270 is capable of writing a data after correction, in the course of reading consecutive data. 532 and 542 are a read mode line showing that consecutive data are read and a write mode line showing that consecutive data are written, respectively, and 552 and 572 are a write command line to a disk and a read command line, respectively. 551 and 571 are WRITE GATE and READ GATE signal lines which are given finally to the disk, respectively. When a correction is completed, a signal line 261 becomes ''1'', and an input condition of an AND element 530 is formed. Therefore, a signal line 531 becomes ''1'', and control by the write command line can be executed through an output 541 of an OR element 540.
摘要翻译：目的：执行自我预防和保存数据，而不会造成软件的负担和吞吐量的下降，同时通过在纠错后自动写入正确的数据来抑制处理属性的下降，错误是在检测到读取错误并被更正的情况下生成。构成：通过门530-570和或非门260,270的触发器电路在读取连续数据的过程中能够在校正之后写入数据。 532和542是分别读取连续数据的读取模式行和表示连续数据被写入的写入模式行，并且552和572分别是对盘和读取命令行的写入命令行。 551和571分别是最后给予磁盘的写入门和读取门信号线。当校正完成时，信号线261变为“1”，并且形成AND元件530的输入条件。因此，信号线531变为“1”，并且可以通过OR元件540的输出541执行写入命令行的控制。

10. 发明专利

JPS58161021A CONTROLLING SYSTEM OF OUTPUT DEVICE 失效
公开(公告)号：JPS58161021A
公开(公告)日：1983-09-24
申请号：JP4263582
申请日：1982-03-19
申请人： HITACHI LTD
发明人： AOKI YOSHIHIKO , OONUMA KUNIHIKO
IPC分类号： G06F13/10 , G06F11/00
摘要： PURPOSE:To report the presence or the absence of abnormality of an output device from a computer to a user, by detecting an undefined code sent to the output device by a controller and reporting the detection result to the computer. CONSTITUTION:In case that a CPU1 selects a controller 2 and tries to transmit data to a typewriter T/W4, the abnormality is reported to the controller and the controller reports the abnormality to the CPU1 if the T/W4 is abnormal. When the CPU1 switches the output device to be used to a line printer L/P5 and discriminates that the L/P5 is not abnormal, data is transmitted from the CPU1 to the L/P5 through a controller 3. This data code is the code for the T/W4; and if it is different from the code for the L/P5, the controller 3 detects the abnormality of the code and opens a gate 7 and reports it to the CPU1. Then, the CPU1 outputs prescribed data to the L/P5 through the controller 3. The user sees the output to find the undefined code.

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