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    • 3. 发明专利
    • Rotable body magnetic memory device
    • 可旋转的身体磁性记忆装置
    • JPS5963015A
    • 1984-04-10
    • JP17318682
    • 1982-10-04
    • Hitachi Ltd
    • TANJI MASAYUKINAKAMURA KUNIOOONUMA KUNIHIKO
    • G06F3/06G11B20/18
    • G11B20/1816
    • PURPOSE:To execute self-prevention and preservation of a data without the burden of a software and a drop of the throughput, and also to suppress a drop of the processing property by writing automatically a correct data after correction in a part where an error is generated, in case when a read error is detected and it is corrected. CONSTITUTION:A flip-flop circuit by gates 530-570 and NOR gates 260, 270 is capable of writing a data after correction, in the course of reading consecutive data. 532 and 542 are a read mode line showing that consecutive data are read and a write mode line showing that consecutive data are written, respectively, and 552 and 572 are a write command line to a disk and a read command line, respectively. 551 and 571 are WRITE GATE and READ GATE signal lines which are given finally to the disk, respectively. When a correction is completed, a signal line 261 becomes ''1'', and an input condition of an AND element 530 is formed. Therefore, a signal line 531 becomes ''1'', and control by the write command line can be executed through an output 541 of an OR element 540.
    • 目的:执行自我预防和保存数据,而不会造成软件的负担和吞吐量的下降,同时通过在纠错后自动写入正确的数据来抑制处理属性的下降,错误是 在检测到读取错误并被更正的情况下生成。 构成:通过门530-570和或非门260,270的触发器电路在读取连续数据的过程中能够在校正之后写入数据。 532和542是分别读取连续数据的读取模式行和表示连续数据被写入的写入模式行,并且552和572分别是对盘和读取命令行的写入命令行。 551和571分别是最后给予磁盘的写入门和读取门信号线。 当校正完成时,信号线261变为“1”,并且形成AND元件530的输入条件。 因此,信号线531变为“1”,并且可以通过OR元件540的输出541执行写入命令行的控制。
    • 4. 发明专利
    • REGISTER DATA READ METHOD
    • JPS5657142A
    • 1981-05-19
    • JP13299679
    • 1979-10-17
    • HITACHI LTD
    • NAKAMURA KUNIO
    • G06F11/32G06F9/22
    • PURPOSE:To make it possible to display arbitray register contents without stop of the on-line processing, by executing the micro program of the control device to read information in the register while the control device is performing control in on- line. CONSTITUTION:The control device refers to the signal of transfer line 17 when entering the idle time; and if transfer request does not come, it enters the decision routine to decide whether the next command instruction has come or not. If transfer request comes, microprocessor 4 fetches data of register address designation register 15 and selects this register file 8 through register address line 18. This output data is set to register data latch circuit 16 through input bus 1, processor 4, and output bus 2 and is displayed by display circuit 21. After that, processor 4 transfers the control to the routine to decide whether the command instruction has come or not. As a result, arbitrary register contents in the control device can be display without stop of the on-line processing, and previous preventive maintenance of the device is possible.
    • 7. 发明专利
    • SYSTEM FOR DOUBLE WRITING FILE
    • JPS6442750A
    • 1989-02-15
    • JP20048487
    • 1987-08-11
    • HITACHI LTD
    • NAKAMURA KUNIO
    • G06F12/16
    • PURPOSE:To decrease the time of writing operation by providing two pairs of data buffer memories to execute an addressing in every other sector so that an address can be made plus one and to store data for one sector and dividing them into the memory for writing operation and the memory for reading operation. CONSTITUTION:The addressing is executed so that the respective sectors of one track and the other track are respectively made plus one in every other sector. Then, the addresses of the sectors to correspond to the respective tracks, to which the same data are written, are physically dislocated for one sector part mutually and the same sector address is obtained. The two pairs of data buffer memories are equipped to have a data storing capacity for one sector and they are divided into the memory for the data writing operation and the memory for the data reading operation. Then, in each sector processing, the writing operation to the data buffer memory and the reading operation are controlled by a magnetic disk control device 2 with being repeated. Thus, the time of the writing operation can be reduced.
    • 9. 发明专利
    • MAGNETIC STORAGE DEVICE
    • JPS5794867A
    • 1982-06-12
    • JP17094880
    • 1980-12-05
    • HITACHI LTD
    • SUZUKI KUNIONAKAMURA KUNIO
    • G06F3/06
    • PURPOSE:To avoid the loss of whole data and at the same time to preserve the latest data, by copying all data to an auxiliary storage device of the backup side immediately after the read errors of a disk occure successively. CONSTITUTION:A magnetic storage device M consists of a magnetic disk device 2, an auxiliary storage device 3 which obtains a backup copy of the device 2 and a controller 4 which controls these devices 2 and 3. The controller 4 detects the presence or absence of a read error of the data when the data is read out of the device 2. Then a retrial action is carried out for reading of the data when an error is detected, and the data of the device 2 is copied to the device 3 when the consecutive frequency of the retrials exceeds a prescribed level. Such device M is connected to a computer 1. Thus an error if occurs during a copying action can be discriminated at the computer side to avoid carrying out a wrong process of data.
    • 10. 发明专利
    • FILE CONTROL UNIT
    • JPS55112663A
    • 1980-08-30
    • JP1967379
    • 1979-02-23
    • HITACHI LTD
    • NAKAMURA KUNIOKUWABARA HIROSHI
    • G06F3/06G06F3/00G06F12/08
    • PURPOSE:To avoid in lowering the entire throughput for the system, by coincident detection between the sector address on the rotary memory unit designated from the processor with the sector address read out from the rotary memory unit. CONSTITUTION:In the data transfer between the processor 100 and the rotary magnetic memory unit 200 having the sector format of the fixed length, the sector address on the unit 200 designated from the processor 100 and the sector address read out from the unit 200 are compared for coincidence detection. Further, after designating the data write-in or readout to the buffer memories 5 and 6 and the confirmation of all the data accessed on the memories 5 and 6, if address coincidence detection is present, the data transfer is controlled between the units 100 and 200 via the memories 5 and 6 in response to the access mode designation output. Thus, if data transfer is disable due to lowering in the data processing ability of the unit 100, the lowering in the throughput of the entire system can be avoided.