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1. 发明专利

JP2013039614A Deformed cross-section structure and method for manufacturing the same 审中-公开
标题翻译：变形的横截面结构及其制造方法
公开(公告)号：JP2013039614A
公开(公告)日：2013-02-28
申请号：JP2011179643
申请日：2011-08-19
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI
IPC分类号： B21B1/08 , B21B1/42 , B21H8/00 , B24B7/13
摘要： PROBLEM TO BE SOLVED: To provide a deformed cross-section structure that improves quality caused by a reduction of surface roughness, and prevents poor surface roughness to reduce the manufacturing cost, and to provide a method for manufacturing the same.SOLUTION: The deformed cross-section structure 32 is formed by a plate bar 23 being rolled, and includes a step 33 formed of a thin plate 31 and a thick plate 30 on a surface thereof. On a rear surface of the deformed cross-section structure, which is a boundary 34 between the thin plate 31 and a thick 30, a region 61 which has different surface roughness from other part and a width of 5 mm or longer is formed across the longitudinal direction.
摘要翻译：要解决的问题：提供一种变形的横截面结构，其提高由表面粗糙度降低引起的质量，并且防止较差的表面粗糙度以降低制造成本，并提供其制造方法。解决方案：变形的横截面结构32由被轧制的板条23形成，并且包括在其表面上由薄板31和厚板30形成的台阶33。在薄板31和厚30之间的边界34的变形横截面结构的后表面上形成有与其他部分不同的表面粗糙度和5mm以上的宽度的区域61 纵向。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2006312212A Grinding method and grinding device 审中-公开
标题翻译：研磨方法和研磨装置
公开(公告)号：JP2006312212A
公开(公告)日：2006-11-16
申请号：JP2005135759
申请日：2005-05-09
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： WATANABE NOBUFUMI , IKEDA TAKESHI
IPC分类号： B24B49/16
摘要： PROBLEM TO BE SOLVED: To provide a grinding method and a grinding device capable of stabilizing a grinding volume, preventing cracks of a ground sample, and supplying a ground product with high accuracy.
SOLUTION: In this method, a ground sample 1 is rotated by a first motor 2, and a grinding tool 3 contacting the ground sample 1 is rotated by a second motor 4, so as to grind the ground sample 1. A grinding resistance generated between the ground sample 1 and the grinding tool 3 is detected as a power volume of the second motor 4, so as to control the first motor 2 according to the power volume.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够稳定研磨体积的磨削方法和研磨装置，防止研磨样品的裂纹，并且高精度地供给磨碎的产品。解决方案：在该方法中，研磨样品1由第一电动机2旋转，接触样品1的研磨工具3通过第二电动机4旋转，从而研磨研磨样品1.研磨作为第二电动机4的动力容积，检测出研磨样品1与研磨工具3之间产生的电阻，以便根据电力量来控制第一电动机2。版权所有（C）2007，JPO＆INPIT

3. 发明专利

JP2006093274A Wafer container 审中-公开
标题翻译： WAFER CONTAINER
公开(公告)号：JP2006093274A
公开(公告)日：2006-04-06
申请号：JP2004274668
申请日：2004-09-22
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI
IPC分类号： H01L21/673 , B65D25/10 , B65D25/20 , B65D85/86
摘要： PROBLEM TO BE SOLVED: To prevent mutual contact of wafers by sustaining a constant space between wafers contained in slots, and to facilitate handling work. SOLUTION: In the container (1) of box structure having at least one open side (1a), slots (4) composed of holding grooves (3) each containing one wafer-like article are provided in a pair of opposing inner walls, and when the wafer container is set laterally, the wafer-like article (W) becomes oblique in the container and a constant space is attained between the wafer-like articles contained in the slots. When the wafer container is set vertically while grounding the outer surface of a sidewall (1e) in which the holding grooves (3) are not formed, outer surface of that sidewall (1e) becomes substantially parallel with the holding grooves (3) so that the contained wafer (W) becomes substantially horizontal. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：通过在狭槽中容纳的晶片之间维持恒定的空间来防止晶片的相互接触，并且便于处理工作。解决方案：在具有至少一个开口侧（1a）的盒结构的容器（1）中，在一对相对的内侧设置有由包含一个晶片状制品的保持槽（3）构成的槽（4）壁，并且当晶片容器横向设置时，晶片状物品（W）在容器中变得倾斜，并且在包含在槽中的晶片状物品之间达到恒定的空间。当在没有形成保持槽（3）的侧壁（1e）的外表面接合晶片容器时，该侧壁（1e）的外表面与保持槽（3）基本平行，使得容纳的晶片（W）变得基本上水平。版权所有（C）2006，JPO＆NCIPI

4. 发明专利

JP2004200527A Method for processing semiconductor wafer 审中-公开
公开(公告)号：JP2004200527A
公开(公告)日：2004-07-15
申请号：JP2002369116
申请日：2002-12-20
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI , MASUYAMA SHOJI
IPC分类号： B24B9/00 , H01L21/02 , H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a method for processing a semiconductor wafer, capable of preventing the occurrence of chipping which is likely to occur, at a portion where a cleavage surface and a front and back surface intersect with each other, when the front and back surface of the semiconductor wafer having the cleavage surface are lapped. SOLUTION: In the method for processing the semiconductor wafer, a cleavage surface 1c is formed on the outer periphery of a semiconductor wafer 1; chamfering is performed to at least either of a front surface 1a side or a back surface 1b side of the semiconductor wafer 1 of the cleavage surface 1c; at least one of the front surface 1a and the back surface 1b of the chamfered semiconductor wafer 1 is lapped. At least either of a front surface side angular part or a back surface side angular part, at a portion where the cleavage surface 1c formed in the outer periphery of the semiconductor wafer 1 and the front and back surfaces 1a, 1b of the semiconductor wafer 1 intersect with each other, is chamfered down to a lapping depth or to the final polishing depth of the front surface 1a or the back surface 1b of the semiconductor wafer 1. COPYRIGHT: (C)2004,JPO&NCIPI

5. 发明专利

JP2004128178A Spin drier 审中-公开
公开(公告)号：JP2004128178A
公开(公告)日：2004-04-22
申请号：JP2002289551
申请日：2002-10-02
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI , MASUYAMA SHOJI
IPC分类号： H01L21/304
摘要： PROBLEM TO BE SOLVED: To provide a spin drier which generates no linear stain on a dried wafer when drying a wafer in a process of manufacturing a wafer with a mirror plane by polishing a sliced wafer obtained by slicing a crystal ingot in a multiple stages.
SOLUTION: For a wafer pasting member to be used for setting the wafers 11 in the spin drier 30, an annular pasting plate 10 having such a shape that a central portion 12 which is not to be used for pasting wafers 11 is removed is fabricated. The wafers 11 with a rough mirror plane are pasted to the annular pasting plate 10 and then are mechanically and chemically polished and washed. Thereafter, these wafers 11 are set in the spin drier 30 and are dried with no linear stain generated thereon.
COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2012020934A Method for producing nitride semiconductor substrate 有权
标题翻译：生产氮化物半导体基板的方法
公开(公告)号：JP2012020934A
公开(公告)日：2012-02-02
申请号：JP2011231199
申请日：2011-10-21
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： MEGURO TAKESHI , SUZUKI TAKAMASA , IKEDA TAKESHI
IPC分类号： C30B29/38 , C30B25/18 , H01L33/32
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a nitride semiconductor substrate capable of producing the nitride semiconductor substrate with a small variation in off-axis angle.SOLUTION: The method for producing a nitride semiconductor substrate comprises forming a nitride semiconductor layer (2) on a sapphire substrate (1) and fabricating a self-standing nitride semiconductor substrate (3) by using the nitride semiconductor layer (2) separated from the sapphire substrate (1), wherein the C-axes are inclined in advance in a radially-outward direction on a front surface of the sapphire substrate (1), so as to cancel inclinations of the C-axes of the nitride semiconductor layer (2) in a radially-inward direction caused by warpage due to a difference in defect density of front/back surfaces of the separated nitride semiconductor layer (2).
摘要翻译：解决的问题：提供一种能够制造偏离角度偏差小的氮化物半导体衬底的氮化物半导体衬底的制造方法。解决方案：制造氮化物半导体衬底的方法包括：在蓝宝石衬底（1）上形成氮化物半导体层（2），并通过使用氮化物半导体层（2）制造自立氮化物半导体衬底（3）与蓝宝石衬底（1）分离，其中C轴在蓝宝石衬底（1）的前表面上沿径向向外的方向预先倾斜，以消除氮化物半导体的C轴的倾斜度由于分离的氮化物半导体层（2）的前/后表面的缺陷密度差引起的翘曲引起的沿着径向向内方向的层（2）。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2012011420A Method of manufacturing deformed cross-section strip material 审中-公开
标题翻译：制造变形交叉条带材料的方法
公开(公告)号：JP2012011420A
公开(公告)日：2012-01-19
申请号：JP2010149814
申请日：2010-06-30
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI
IPC分类号： B21B1/08 , B21B1/42 , B21H8/00
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a deformed cross-section strip material capable of reducing variation in plate thickness that occurs at the start of working after coil exchange, to prevent occurrence of failure at the time of finish rolling, resulting in improved yield and reduced manufacturing cost.SOLUTION: A deformed cross-section strip material manufacturing device 70 is equipped with a planar V-shape die 60 including protruding parts 61a and 61b whose rolling work surface is widened toward the end from a tip side in V-shape, and a planetary rolling roll 71 that is provided to face the rolling work surface of the planar V-shape die 60. A plate-like strip material 73 is introduced between the planar V-shape die 60 and the planetary rolling roll 71 by using the device 70 and the plate-like strip material 73 is rolled to be the variant cross-section bar material 82. Here, the planar V-shape die 60 is provided with a temperature adjusting mechanism 1, to prevent dropping of temperature of the planar V-shape die 60 at the time when the deformed cross-section strip material manufacturing device 70 stops.
摘要翻译：解决问题的方案：提供一种制造变形的横截面带材的方法，该方法能够减少在线圈更换之后开始工作时发生的板厚变化，以防止精轧时发生故障，从而提高产量并降低制造成本。解决方案：变形的横截面带状材料制造装置70装备有平面V形模具60，该平面V形模具60包括其V形的顶端侧的滚动工作面向其端部变宽的突出部61a和61b，以及行星滚筒71设置成面对平面状V字形模具60的滚动工作面。板状条带材73通过使用该装置向平面V型模具60和行星滚动辊71之间引入 70，并且板状条带材料73被轧制成变形横截面棒材料82.这里，平面V形模具60设置有温度调节机构1，以防止平面V形模具60的温度下降。当变形的横截面带状材料制造装置70停止时，成形模具60。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2010042958A Method for producing group iii-v nitride semiconductor substrate 有权
标题翻译：用于生产III-V族氮化物半导体衬底的方法
公开(公告)号：JP2010042958A
公开(公告)日：2010-02-25
申请号：JP2008208022
申请日：2008-08-12
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI , MEGURO TAKESHI
IPC分类号： C30B29/38 , C23C16/01 , C23C16/34 , C30B25/18 , H01L33/32
摘要： PROBLEM TO BE SOLVED: To provide a method for producing a group III-V nitride semiconductor substrate reducing the distribution of inclination of crystal axes within the face of the group III-V nitride semiconductor substrate. SOLUTION: The method for producing a group III-V nitride semiconductor substrate includes heteroepitaxially growing a group III-V nitride semiconductor crystal on the following heterogeneous substrate 1. In the heterogeneous substrate 1, an inclination angle α of a crystal axis (a) of a crystal face as a reference of the heterogeneous substrate 1 with respect to the normal line (n) of the heterogeneous substrate surface 1a, and an inclination angle η of the crystal axis (a) at a position P of 20 mm distant in the radial direction from the center O of the heterogeneous substrate 1 with respect to the normal line (n) of the heterogeneous substrate surface 1a satisfy a relationship of 0.02° COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种减少III-V族氮化物半导体衬底的表面内的晶轴的倾斜分布的III-V族氮化物半导体衬底的制造方法。解决方案：用于制造III-V族氮化物半导体衬底的方法包括在随后的异质衬底1上异质外延生长III-V族氮化物半导体晶体。在非均相衬底1中，晶轴的倾斜角 a）作为异质衬底1相对于非均相衬底表面1a的法线（n）的参考的晶面以及在距离为20mm的位置P处的晶轴（a）的倾斜角度η 在异质衬底1的中心O相对于异质衬底表面1a的法线（n）的径向方向上，满足0.02°<¾η-α¾的关系以及每个的晶体轴（a）衬底表面1a内的点相对于衬底表面1a的法线（n）在异质衬底1的径向方向上向外倾斜。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2009295767A Marking method of nitride semiconductor substrate, and nitride semiconductor substrate 有权
标题翻译：氮化物半导体衬底和氮化物半导体衬底的标记方法
公开(公告)号：JP2009295767A
公开(公告)日：2009-12-17
申请号：JP2008147615
申请日：2008-06-05
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI
IPC分类号： H01L21/02 , B23K26/00
摘要： PROBLEM TO BE SOLVED: To provide a marking method of a nitride semiconductor substrate, which is capable of marking a surface of a nitride semiconductor substrate by a laser beam of a prescribed wavelength region including a fundamental wave and a second harmonic wave of Nd-YAG laser, and to provide a nitride semiconductor substrate. SOLUTION: The marking method of a nitride semiconductor substrate includes: a substrate preparation step of preparing a nitride semiconductor substrate having a first surface being a mirror surface and a second surface facing the first surface; and a marking step of irradiating the substrate from the first surface side with a laser beam at a wavelength of 450 to 1,100 nm to form a mark having a prescribed depth from the first surface toward the second surface in an area irradiated with the laser beam. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种氮化物半导体衬底的标记方法，该方法能够通过包括基波和第二谐波的规定波长区域的激光束来标记氮化物半导体衬底的表面， Nd-YAG激光器，并提供氮化物半导体衬底。解决方案：氮化物半导体衬底的标记方法包括：准备氮化物半导体衬底的衬底制备步骤，所述氮化物半导体衬底具有第一表面和第二表面，第一表面是镜面，第二表面面向第一表面; 以及标记步骤，用450〜1100nm波长的激光束从第一表面侧照射基板，以在照射激光束的区域中形成从第一表面朝向第二表面的具有规定深度的标记。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2006339431A Method of processing nitride semiconductor substrate 审中-公开
标题翻译：加工氮化物半导体基板的方法
公开(公告)号：JP2006339431A
公开(公告)日：2006-12-14
申请号：JP2005162681
申请日：2005-06-02
申请人： Hitachi Cable Ltd , 日立電線株式会社
发明人： IKEDA TAKESHI , MASUYAMA SHOJI
IPC分类号： H01L21/304 , B26F1/26
摘要： PROBLEM TO BE SOLVED: To provide a method of processing a nitride semiconductor substrate capable of drastically shortening a contour processing time of an independent type nitride semiconductor substrate.
SOLUTION: First, a substrate 1 of a circular independent type GaN grown by an HVPE method, etc. is prepared. A mark-off line 2 is provided to the substrate 1 in parallel to a crystal azimuth for performing an OF process by use of an X-ray diffraction instrument. Next, after the substrate 1 is set so as to make the mark-off line 2 of the substrate 1 parallel with a straight part of an OF 3a of a tool 3 for performing ultrasonic process, the ultrasonic process is performed. Thus, the substrate 1 is precisely hollowed out in a circle having a flat OF and IF complying with a shape of the tool 3. Thus, the OF process, the IF process and an outer diameter process can be simultaneously performed.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够显着缩短独立型氮化物半导体衬底的轮廓处理时间的氮化物半导体衬底的处理方法。解决方案：首先，制备通过HVPE法等生长的圆形独立型GaN的衬底1。与使用X射线衍射仪进行OF处理的晶体方位并行地向基板1设置标记线2。接下来，在将基板1设定为使得基板1的标记线2与用于进行超声波处理的工具3的直线部分的平行部分平行的情况下，执行超声波处理。因此，基板1被精确地挖成圆形，具有平坦的OF和IF，符合工具3的形状。因此，可以同时执行OF工艺，IF工艺和外径工艺。版权所有（C）2007，JPO＆INPIT

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