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1. 发明专利

JP2009224714A Manufacturing method of organic thin film transistor 有权
标题翻译：有机薄膜晶体管的制造方法
公开(公告)号：JP2009224714A
公开(公告)日：2009-10-01
申请号：JP2008070082
申请日：2008-03-18
申请人： Harima Chem Inc , Sij Technology:Kk , Univ Of Tokyo , ハリマ化成株式会社 , 国立大学法人東京大学 , 株式会社エスアイジェイテクノロジ
发明人： SOMEYA TAKAO , SEKIYA TAKESHI , MURATA KAZUHIRO , MATSUBA YORISHIGE , KOYAMA MASAHIDE
IPC分类号： H01L29/786 , H01L21/336 , H01L51/05 , H01L51/30 , H01L51/40
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of an organic thin film transistor, capable of producing a source electrode and a drain electrode configuring an organic thin film transistor by utilizing the dispersion solution of metal nanoparticles in which an organic solvent is a dispersion solvent. SOLUTION: In the process of forming the source electrode and the drain electrode, a metal nanoparticle dispersion solution is applied in a prescribed pattern shape to form a metal nanoparticle dispersion solution application layer using an ultrafine inkjet printer, the metal nanoparticle dispersion solution application layer is heated and sintered, and the source electrode and the drain electrode consisting of a metal nanoparticle sintered body layer are formed. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种有机薄膜晶体管的制造方法，其能够通过利用金属纳米颗粒的分散溶液来生产构成有机薄膜晶体管的源电极和漏电极，其中有机溶剂是分散溶剂。解决方案：在形成源电极和漏电极的过程中，以规定的图案形状施加金属纳米颗粒分散液，以使用超细喷墨打印机形成金属纳米颗粒分散液施加层，金属纳米颗粒分散溶液施加层被加热烧结，并且形成由金属纳米颗粒烧结体层组成的源电极和漏电极。版权所有（C）2010，JPO＆INPIT

2. 发明专利

JP2005293937A Method of forming metal thin-film layer on conductive ito film or on glass substrate surface as base substrate of ito film, and metal thin-film layer on conductive ito film or on glass substrate surface as base substrate of the ito film 有权
标题翻译：在导电ITO膜上形成金属薄膜层的方法或作为ITO膜的基底表面的玻璃基底表面上形成金属薄膜层的方法，以及导电ITO膜上的金属薄膜层或作为ITO膜的基板的玻璃基板表面的方法
公开(公告)号：JP2005293937A
公开(公告)日：2005-10-20
申请号：JP2004104791
申请日：2004-03-31
申请人： Harima Chem Inc , Ulvac Japan Ltd , ハリマ化成株式会社 , 株式会社アルバック
发明人： UEDA MASAYUKI , KOYAMA MASAHIDE , HATA NORIAKI , MATSUBA YORISHIGE , IWASHIGE HIROSHI , ODA MASAAKI
IPC分类号： G02F1/1343 , C03C17/34 , H01B5/14 , H01B13/00
摘要： PROBLEM TO BE SOLVED: To provide a method, capable of forming a fine metal thin film pattern excellent in adherence properties on the surface of a conductive ITO film and a glass substrate of a base substrate, with high drawing precision, high workability, and high reproducibility. SOLUTION: The thin film layer of transition metal is formed by applying a solvent formed by dissolving transition metal compound, containing organic anion and cation of transition metal in organic solvent on the ITO film and on the surface of the glass substrate of a base substrate, and applying heat treatment thereto. The fine metal thin-film pattern with superior adherence properties is formed on the surface of the transition metal thin film layer, by applying a liquid, in which metal fine particles with average size of 1 to 100 nm are dispersed at a prescribed thickness, and by forming a layer in which fine metal particles are sintered mutually, by heating and sintering the above. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决问题的方案：提供一种能够在导电性ITO膜和基材的玻璃基板的表面上形成粘合性优异的金属薄膜图案，拉拔精度高，加工性高的方法，重现性高。解决方案：过渡金属的薄膜层通过将通过将含有有机阴离子的过渡金属化合物和过渡金属的阳离子溶解在有机溶剂中而形成的溶剂形成在ITO膜上和玻璃基板的表面上并对其进行热处理。在过渡金属薄膜层的表面上，通过涂布以规定厚度分散平均粒径为1〜100nm的金属微粒子的液体，形成具有优异粘附特性的金属薄膜图案，通过加热和烧结上述方法形成相互烧结金属微粒的层。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2003347718A Surface mounting method and circuit board 审中-公开
标题翻译：表面安装方法和电路板
公开(公告)号：JP2003347718A
公开(公告)日：2003-12-05
申请号：JP2002155404
申请日：2002-05-29
申请人： Harima Chem Inc , ハリマ化成株式会社
发明人： KOYAMA MASAHIDE , MATSUBA YORISHIGE , TERADA NOBUHITO , IZUMITANI AKITO
IPC分类号： B23K35/363 , H01L21/60 , H05K3/34
摘要： PROBLEM TO BE SOLVED: To provide a surface mounting method in which an underfill agent which utilizes a thermo-plastic resin is added with flux activity, and capable of soldering and flux processing to a solder material under the flux activity in a single thermal process. SOLUTION: A thermo-plastic resin that contains, as a main component, an atom group showing flux property in molecule is used as a sealing filler, and the one that softens or melts at the melting point of a solder material is selected. The atom group showing the flux property acts to remove the oxide film of a metal material constituting a bump or a pad provided on the substrate as well as the surface mounting components contacting the thermo-plastic resin. A blind via is eccentrically positioned on the pad for a reproducible good solder joint and sealing/filling, in a single process. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种表面安装方法，其中使用热塑性树脂的底部填充剂添加有助焊剂活性，并且能够以单一的助焊剂活性焊接和焊剂加工到焊料材料热处理。解决方案：使用包含分子中显示焊剂性质的原子团作为主要成分的热塑性树脂作为密封填料，并且选择在焊料的熔点下软化或熔化的材料。显示助焊剂性质的原子团起到除去构成凸起的金属材料的氧化物膜或者设置在基板上的焊盘以及与热塑性树脂接触的表面安装部件的作用。盲孔通过偏心定位在垫上，用于可重复的良好焊接接头和密封/填充，在单个过程中。版权所有（C）2004，JPO

4. 发明专利

JP2008016729A Manufacturing method for semiconductor device with double-sided electrode structure 有权
标题翻译：具有双面电极结构的半导体器件的制造方法
公开(公告)号：JP2008016729A
公开(公告)日：2008-01-24
申请号：JP2006188289
申请日：2006-07-07
申请人： Harima Chem Inc , Kyushu Institute Of Technology , Sijtechnology Inc , ハリマ化成株式会社 , 国立大学法人九州工業大学 , 株式会社Sijテクノロジ
发明人： ISHIHARA MASAMICHI , KOYAMA MASAHIDE
IPC分类号： H01L23/12 , H01L23/50 , H01L25/00
CPC分类号： H01L25/16 , H01L24/73 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/19105 , H01L2924/19106 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide an inexpensive semiconductor device with a double-sided electrode structure that can be simply manufactured without requiring a through-electrode technology, and to provide its manufacturing method. SOLUTION: A circuit element including a semiconductor chip is arranged so as to be resin-molded. Each external connection electrode connected to the circuit element is arranged on both faces of the front face and the rear face. The circuit element is arranged on an organic substrate so as to connect it with a wiring pattern provided on the organic substrate. Each one end of a plurality of internal connection electrodes integrally composed by a connecting plate is connected to a prescribed position on the wiring pattern. After the circuit element is resin-molded, the front-face side is planarized by polishing or grinding the front-face side until the connecting plate is eliminated so as to compose a plurality of the internal connection electrodes into an individual internal connection electrode while separating a plurality of the internal connection electrodes from each other. Each of the other end of a plurality of the internal connection electrodes is used as the external connection electrode on the front face. Each external connection electrode on the rear face is connected to the wiring pattern via a conductive layer inside a through hole provided in the organic substrate. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有双面电极结构的便宜的半导体器件，其可以简单地制造而不需要通过电极技术，并提供其制造方法。解决方案：包括半导体芯片的电路元件被布置成树脂模制。连接到电路元件的每个外部连接电极布置在前表面和后表面的两个面上。电路元件设置在有机基板上，以将其连接到设置在有机基板上的布线图案。由连接板一体地组成的多个内部连接电极的每一端连接到布线图案上的规定位置。在电路元件被树脂模制之后，通过抛光或研磨正面侧来平面化正面侧，直到连接板被去除，以便将多个内部连接电极组成单独的内部连接电极，同时分离多个内部连接电极彼此。多个内部连接电极的另一端各自用作正面上的外部连接电极。后表面上的每个外部连接电极经由设置在有机基板中的通孔内的导电层连接到布线图案。版权所有（C）2008，JPO＆INPIT

5. 发明专利

JP2004095615A Method for surface mounting and circuit board 审中-公开
公开(公告)号：JP2004095615A
公开(公告)日：2004-03-25
申请号：JP2002250968
申请日：2002-08-29
申请人： Harima Chem Inc , ハリマ化成株式会社
发明人： KOYAMA MASAHIDE , MATSUBA YORISHIGE , TERADA NOBUHITO , IZUMITANI AKITO
IPC分类号： H01L21/60
CPC分类号： H01L24/81 , H01L2924/00011 , H01L2924/01322 , H01L2924/351 , H01L2924/00 , H01L2224/81805
摘要： PROBLEM TO BE SOLVED: To provide a means for suppressing cracks in soldered joints between solder bumps of surface-mount components and electrode pads on a substrate due to a stress strain during the heat cycle in a flip-chip mounting method. SOLUTION: A thermoplastic resin composition is added with a flux activity. An application film of the thermoplastic resin composition is formed on tops of the solder bumps in advance, and then a heat treatment is carried out in a reflow process. By this method, an oxide film of a metal material such as a solder material can be eliminated by the flux activity of the thermoplastic resin composition, and hence good-conditioned solder bonding can be performed. Thereafter, when cooled, the thermoplastic resin covering the periphery of the joints is solidified and becomes a resin coat/adhesive layer, exhibiting a crack suppressing effect to materialize more powerful solder bonding. COPYRIGHT: (C)2004,JPO

6. 发明专利

JP2008100235A Treatment method for lead-free solder alloy 有权
标题翻译：无铅焊接合金的处理方法
公开(公告)号：JP2008100235A
公开(公告)日：2008-05-01
申请号：JP2006282711
申请日：2006-10-17
申请人： Harima Chem Inc , Kyushu Institute Of Technology , ハリマ化成株式会社 , 国立大学法人九州工業大学
发明人： IZUMI AKIRA , KOYAMA MASAHIDE , KUMAMOTO SATOSHI
IPC分类号： B23K35/26 , B22F1/00 , C22C13/00
摘要： PROBLEM TO BE SOLVED: To provide a lead-free solder raw material having a low melting point and uniform particle sizes.
SOLUTION: Regarding the treatment method for a lead-free solder alloy, using atomic hydrogen generated by a hot wire process, a lead-free solder alloy is subjected to reduction and etching. In the other mode, by a hot wire process, a lead-free solder alloy is treated with a nitrogen compound, so as to form a thermally instable nitride film on the surface thereof.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供具有低熔点和均匀粒径的无铅焊料原料。解决方案：关于无铅焊料合金的处理方法，使用通过热丝工艺产生的原子氢，对无铅焊料合金进行还原和蚀刻。在另一种模式中，通过热丝工艺，用氮化合物处理无铅焊料合金，以在其表面上形成热不稳定的氮化物膜。版权所有（C）2008，JPO＆INPIT

7. 发明专利

JP2009021600A Circuit pattern 审中-公开
标题翻译：电路图案
公开(公告)号：JP2009021600A
公开(公告)日：2009-01-29
申请号：JP2008181156
申请日：2008-07-11
申请人： Harima Chem Inc , ハリマ化成株式会社
发明人： IRIE HISAO , KOYAMA MASAHIDE
IPC分类号： H05K3/34
摘要： PROBLEM TO BE SOLVED: To enhance bonding accuracy of chip components on an electrode of a circuit pattern.
SOLUTION: In the circuit pattern, a wiring pattern is covered with solder resist, and a region of the wiring pattern exposed from the solder resist serves as the electrode. The electrode is formed to have only one portion with the maximum width along the right and left length direction. Specifically, the width of the electrode is continuously thinned toward right and left both ends in the length direction, and is continuously widened toward the center in the length direction. Since molten solder is collected toward the portion with the maximum length on the electrode, dispersion of the collecting portion of the solder in the length direction of the electrode is eliminated. This can enhance bonding accuracy of the chip components on the electrode and improve mounting reliability.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提高电路图案的电极上的芯片部件的接合精度。解决方案：在电路图案中，布线图案被阻焊剂覆盖，并且从阻焊剂露出的布线图案的区域用作电极。电极形成为仅具有沿着左右长度方向具有最大宽度的一部分。具体地，电极的宽度在长度方向上的左右两端连续变薄，并且在长度方向上朝向中心连续变宽。由于熔融焊料朝向电极上具有最大长度的部分收集，消除了焊料在电极长度方向上的收集部分的分散。这可以提高电极上的芯片部件的接合精度并提高安装可靠性。版权所有（C）2009，JPO＆INPIT

8. 发明专利

JP2007123558A Solder bump forming method 有权
标题翻译：焊膏形成方法
公开(公告)号：JP2007123558A
公开(公告)日：2007-05-17
申请号：JP2005313772
申请日：2005-10-28
申请人： Harima Chem Inc , ハリマ化成株式会社
发明人： KOYAMA MASAHIDE , KUKIMOTO YOICHI , SAKURAI HITOSHI
IPC分类号： H01L21/60
CPC分类号： H01L2224/16225
摘要： PROBLEM TO BE SOLVED: To provide a method of forming a solder bump that is excellent in reliability of bonding with a semiconductor chip. SOLUTION: This method is that a bump 30 is formed on the surfaces of two or more electrodes 14 exposed in the opening 13 of a solder resist layer 12 deposited on the surface of a substrate 11. The method comprises processes of extending the opening 13 out of a vertical projected area so as to position it out of the vertical projected area of a semiconductor chip that is connected to the exposed one terminals of the electrodes 14, forming a resin mask layer 21 on the exposed part of the electrode except the solder bump bonder 20 of the semiconductor chip, forming the solder bump 30 by filling the surfaces of the electrodes 14 at the solder bump bonder 20 with a solder paste composition and heating the solder paste composition, and removing the resin mask layer 21 after the solder bump 30 is formed. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种形成与半导体芯片的接合的可靠性优异的焊料凸块的方法。解决方案：该方法是在沉积在基板11的表面上的阻焊层12的开口13中露出的两个或更多个电极14的表面上形成凸点30。将其从垂直投影区域中的开口13排出，以将其定位在与电极14的暴露的一个端子连接的半导体芯片的垂直投影区域中，在电极的暴露部分上形成树脂掩模层21，除了半导体芯片的焊料凸块接合器20，通过用焊膏组合物填充焊料凸块焊接机20的电极14的表面，并加热焊膏组合物，形成焊料凸块30，并且在其后除去树脂掩模层21 形成焊料凸块30。版权所有（C）2007，JPO＆INPIT

9. 发明专利

JP2004319676A Solder deposition method and solder bump forming method 有权
公开(公告)号：JP2004319676A
公开(公告)日：2004-11-11
申请号：JP2003110125
申请日：2003-04-15
申请人： Harima Chem Inc , ハリマ化成株式会社
发明人： KUKIMOTO YOICHI , SAKURAI HITOSHI , KUMAMOTO SATOSHI , KOYAMA MASAHIDE
IPC分类号： B23K35/22 , B23K35/26 , B23K35/34 , B23K35/363 , H01L21/60 , H01L23/12 , H05K3/34
CPC分类号： H01L24/12 , H01L24/11 , H01L2224/05573 , H01L2224/1147 , H01L2224/11472 , H01L2224/13011 , H01L2224/13099 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01015 , H01L2924/01019 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H05K3/3484 , H05K2203/043 , H05K2203/0588 , H05K2203/1163 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To provide a solder deposition method which can deposit solder having a desired height precisely and simply and prevent generation of void, and to provide a solder bump forming method using the solder deposition method. SOLUTION: The solder deposition method comprises a process for forming a dam to ambients of an electrode on a substrate, a process for spread deposition type solder formulation on the substrate, and a process which heats the spread deposition type solder compound and deposits solder on the surface of the electrode. The solder deposition method is suitable for forming a large solder bump with fine pitch. COPYRIGHT: (C)2005,JPO&NCIPI

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