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    • 8. 发明专利
    • MOS SEMICONDUCTOR MANUFACTURING DEVICE
    • JPH06232355A
    • 1994-08-19
    • JP1522393
    • 1993-02-02
    • HITACHI LTD
    • KANETANI TATSUNORIYUMOTO OSAMUMORIGUCHI AKISADATAJIRI KAZUYUKI
    • H01L27/08
    • PURPOSE:To prevent a CMOSIC from being latched up by a method wherein an N-MOS region in the CMOSIC is formed on an N-type region separated electrically from the P region of a substrate and a P-MOS region in the CMOSIC. CONSTITUTION:A single crystal film is formed on a P-semiconductor substrate 1 and SiO2 films 2 for isolation use and channel stoppers 3 are formed. An implantation of N-type impurities, such as phophorus, is performed not only in a P-MOS region but in an N-MOS region and an N-type well region 5 and an N-type region 6 for isolation use are formed. A P-type well region for the N-MOS region is formed in the region 6 by implanting P-type impurities, such as boron, in the region 6. In a reference CMOS inverter circuit, parasitic transistors 10 and 12 constituting a positive feedback circuit are connected to each other via parasitic transistors 11 and 13, a reverse bias is applied to all terminals of the transistors 11 and 13 and the transistors 11 and 13 are never brought in an operating state. Accordingly, the positive feedback circuit is not constituted of the parasitic transistors.