专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明专利

JPH0324725A THIN FILM FORMING METHOD, AND METHOD AND DEVICE FOR MANUFACTURE OF SEMICONDUCTOR 失效
公开(公告)号：JPH0324725A
公开(公告)日：1991-02-01
申请号：JP15818989
申请日：1989-06-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , SHIMIZU AKIHIRO , TERADA TOMOYUKI , SAITO MASAYOSHI
IPC分类号： C23C16/04 , C23C16/06 , H01L21/285 , H01L21/3205
摘要： PURPOSE:To enable excellent metal burying by ionizing reaction species gas of metal to be buried, and applying a voltage of electric potential lower than the cationized reaction species gas to a substrate electrode. CONSTITUTION:Reaction species gas 3 is selectively introduced in the vicinity of a sample from a mixed system of plasma and ionized reaction species gas; a voltage of electric potential lower than the reaction species gas 3 is applied to the sample, thereby performing chemical vapor growth; thus a metal film is selectively formed in a hole 4. That is, when the hole 4 is kept at an electric potential lower than the cationized reaction species gas 3 by using power supplies 8, 9, 9', the reaction species gas 3 is attracted by the electric potential of the bottom of the hole 4, and selectively fly into the hole 4, so that the deposition of reaction product only in the hole 4 is progressed. Thereby the reaction product is highly selectively buried without depending on the base material of the sample or the surface condition, and a thin film can be formed.

2. 发明专利

JPH01242775A FORMATION OF THIN FILM AND DEVICE THEREFOR 失效
公开(公告)号：JPH01242775A
公开(公告)日：1989-09-27
申请号：JP6745088
申请日：1988-03-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , TERADA TOMOYUKI , HONMA YOSHIO , TSUNEKAWA SUKEYOSHI
IPC分类号： C23C14/34 , H01L21/285 , H01L21/31
摘要： PURPOSE:To form a metallic thin film free from cutting on the bottom parts of pier holes without lowering sputtering-etching velocity by allowing the sputtering-etching species produced with glow discharge to make incident at the specified incident angle. CONSTITUTION:A substrate electrode 2 is formed into a network or lattice-like shape and an ion sheath 13 is formed on the surface by glow discharge. At this time, the sputtering-etching species fly in the direction of a substrate holder 4 existing at proper distance and on a sample 5 from the gaps of the substrate electrode 2 while tilting the incident angle for the sample 5 in a range of about zero-90 deg.. The flying energy of the sputtering-etching species is controlled by the DC electric sources 8, 9 besides substrate electric power and further the substrate holder 4 is rotated on its axis and thereby the sputtering-etching species are uniformly made incident on the surface of the sample 5. Thereby a metallic thin film free from cutting on the bottom parts of pier holes can be formed without lowering sputtering-etching velocity.

3. 发明专利

JPH032370A FORMATION OF THIN FILM AND THIN FILM FORMING DEVICE 失效
公开(公告)号：JPH032370A
公开(公告)日：1991-01-08
申请号：JP13603589
申请日：1989-05-31
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , TERADA TOMOYUKI , SASAKI EIJI , TAKAHASHI TOSHIKAZU , NISHIDA TAKASHI , SAITO MASAYOSHI , TSUNEKAWA SUKEYOSHI
IPC分类号： C23C14/34 , H01L21/285
摘要： PURPOSE:To lower the sputter etching speed in the bottom of via hole, etc., and to form a thin film without chipping the bottom by bringing sputter etching species into collision against a sample at an arbitrary angle and allowing the sputter etching to the sample from plural directions. CONSTITUTION:The sputter etching species 7 are attracted or thrusted away by the electric power or magnetic force impressed to an intermediate electrode 5 at the time when the above-mentioned species are made incident perpendicularly on the electrode 5 and pass the electrode as shown in the drawing. As a result, the progressing direction of the sputter etching species 7 is changed and is brought into collision against the sample 4 at the prescribed angle. The angle distribution at which the sputter etching species 7 collide against the sample 4 is adjusted by the intensity of the electric power or magnetic force impressed to the electrode 5 and the bias voltage impressed to the substrate electrode 2. The angle of the collision of the sputter etching species 7 against the sample 4 is accurately controlled in this way and the chipping in the step part of the sample, more particularly the bottom of the via hole, etc., is prevented and the good film covering shape is simultaneously obtd.

4. 发明专利

JPH01109765A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH01109765A
公开(公告)日：1989-04-26
申请号：JP26644587
申请日：1987-10-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI TOSHIKAZU , TERADA TOMOYUKI , SATO AKIRA , HONMA YOSHIO , HINODE KENJI
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L29/43 , H01L29/45 , H01L29/49
摘要： PURPOSE:To improve a contact property with a ground, by using a gas, in which a gas including nitrogen is added to sputtering gas during the formation of a film, and forming a Ti film by sputtering, and including 1-8wt.% nitrogen in the Ti film. CONSTITUTION:Connecting holes 6 are formed in insulating layers 2 and 3, which are deposited on the surface of a semiconductor substrate 1. A Ti film 4 including nitrogen and a TiN (the ratio of the numbers of atoms of Ti and N is about 1:1) film 7 are overlapped and used at least at a part of a conductor wiring layer, which is connected to the semiconductor substrate 1 through the connecting holes 6. At this time, at least one gas of N2 and NF3 is added into a sputtering gas so that the concentration of N included in the formed Ti film 4 becomes 1-8wt.%. The Ti thin film 4 is formed by a sputtering method. Thus peeling and the like of an electrode and the wiring film can be prevented.

5. 发明专利

JPS61267365A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS61267365A
公开(公告)日：1986-11-26
申请号：JP10821785
申请日：1985-05-22
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： ITO MASAHIKO , TERADA TOMOYUKI , YAMAMOTO NAOKI
IPC分类号： H01L29/41 , H01L29/51 , H01L29/46
摘要： PURPOSE:To enable suppression of the silicide reaction even in high-temperature heat treatment as well as formation of an ohmic contact by causing an extremely thin SiO2 barrier film to lie between the gate electrode and the Si substrate. CONSTITUTION:An Si oxide film 2 for separation between the elements and a gate oxide film 3 are formed on a P-type Si substrate 1, and boron ions are implanted into the whole surface. With a photoresist 4 as a mask, arsenic ions for forming a source-drain region are implanted, with the resist 4 as a mask the gate oxide film 3 is removed, and annealing is performed in N2 to activate the impurity in the source-drain region and to form an extremely thin SiO2 film 5 which is the barrier film for the silicide reaction. Then, a film 6 of W, Mo, Ti, Ta or the like is formed as a gate electrode by means of the sputtering process, PSG 7 is deposited, and a contact hole 8 is made. Next, an Al-Si film 9 is deposited, and a passivation film 10 is formed, thus providing a MOS transistor having a direct contact structure.

6. 发明专利

JPH0661169A ION IMPLANTATION ASSIST DEVICE 失效
公开(公告)号：JPH0661169A
公开(公告)日：1994-03-04
申请号：JP20878692
申请日：1992-08-05
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHAMA TAKASHI , HIRAIWA ATSUSHI , USUI HIROO , TERADA TOMOYUKI
IPC分类号： H01L21/265 , H01L21/00
摘要： PURPOSE:To enable the distribution of recoil atom contamination in an ion implanted specimen to be estimated by a method wherein an optional region of the inner wall of an ion implantation device is designated, and the recoil motions of contaminating recoil atoms are traced one by one through a two- body collision approximation Monte Carlo method in the region concerned. CONSTITUTION:An incident angle is determined when an ion beam is applied to an origin of a coordinate system. Then, the hit point of an implanted atom is set adjacent to the origin of the coordinate system. After the hit point of an implanted atom is determined, an ion beam application is executed. First, the scattering angles of incident atoms are determined through a Monte Carlo method. Then, the transition energy T of atom is determined based on its scattering angle theta. The transition energy T is compared with a displacement energy of atom of an ion implantation device inner wall material, and when the inequality, (transition energy)

7. 发明专利

JPH03264672A THIN FILM FORMING METHOD, PRODUCTION OF SEMICONDUCTOR DEVICE AND THIN FILM FORMING DEVICE 失效
公开(公告)号：JPH03264672A
公开(公告)日：1991-11-25
申请号：JP6102590
申请日：1990-03-14
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SATO AKIRA , TERADA TOMOYUKI , SASAKI EIJI
IPC分类号： C23C16/44 , C23C16/52 , H01L21/285 , H01L21/31
摘要： PURPOSE:To form metallic films without any gap even if there is a recess on a substrate at the time of forming the films on the substrate of Si, etc., by CVD method by impressing a bias voltage on the substrate when the film is formed, then stopping the impressing and supplying a fresh raw gas. CONSTITUTION:A high-frequency bias voltage is impressed on a sample obtained by forming an insulating film 2 and a via hole 3 on the surface of an Si substrate 1 by a high-frequency power source 7 through a modulator 6, and a gaseous mixture of WF6 and SiH4 is supplied on the surface. The WF6 in the gas is reduced and decomposed to form a film of metallic W on the substrate surface by CVD method. Since the reacted gas is moved more slowly in the hole 3 than on the flat part and the gas having low contents of WF6, SiH4, etc., is left in the hole, the impressing of the bias voltage is stopped, the gas in the hole is replaced by a fresh raw gas having high contents of WF6 and SiH4, and a bias voltage is again impressed to carry out CVD. Consequently, chemical vapor deposition layers t1-t6 of W4 without any gap are formed even in the recess 3 such as a via hole formed by the substrate 1 and the insulating film 2.

8. 发明专利

JPH01241162A ALUMINUM WIRING OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01241162A
公开(公告)日：1989-09-26
申请号：JP6744988
申请日：1988-03-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKAHASHI TOSHIKAZU , TERADA TOMOYUKI , NISHIDA TAKASHI
IPC分类号： H01L29/43 , H01L21/28
摘要： PURPOSE:To prevent the hillock and the like of aluminum wiring, by depositing nitride films of metals having high melting points such as a nitride titanium film on aluminum and between aluminum films. CONSTITUTION:Contact holes 6 are made, for example, in a phosphorus silicate glass 5 and an aluminum film 7 containing 1wt.%. silicon is formed and then, a nitride titanium film 8 is formed. Further, the aluminum film 7 and the nitride titanium film 8 containing 1wt.%, silicon are formed. In this way, nitride films of metals having the high melting points such as TiN, TaN, ZrN, HfN, and others are formed on aluminum wiring. Reflectance of a metal nitride film having a high melting point with respect to i-rays, g-rays of a mercury lamp is almost equal to reflectance of Si end even reactivity with Al of these nitride films is low. As a result, a heat treatment and the like which are performed after the formation of wiring do not exert influence on Al wiring. Thus, halation in a lithographic process is prevented; besides, electromigration, stress migration, hillock, and the like of aluminum wiring are prevented.

9. 发明专利

JPS63157862A SPUTTERING APPARATUS 失效
公开(公告)号：JPS63157862A
公开(公告)日：1988-06-30
申请号：JP30130086
申请日：1986-12-19
申请人： HITACHI LTD , HITACHI VLSI ENG , ULVAC CORP
发明人： HONMA YOSHIO , HINODE KENJI , TERADA TOMOYUKI , MINAMI AKIRA
IPC分类号： C23C14/34
摘要： PURPOSE:To inhibit deterioration in the quality of films and to enhance a flattening effect, by providing a DC bias circuit to an apparatus for forming films on substrates under applied electric potential. CONSTITUTION:One or more cathodes 21A, 21B are placed in a vacuum vessel 20 and an AC power source 24B is connected to one or more of the cathodes. A DC bias circuit 26 is provided between the cathode 21B on which substrates 22 are set as a substrate electrode and a matching circuit 28B and between the cathode 21B and an earthed electrode. DC potential on the surface of the cathode 21B is arbitrarily controlled with respect to earth potential with the circuit 26 and high quality films are formed on the substrates 22.

10. 发明专利

JP2000237155A MICROELECTRODE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000237155A
公开(公告)日：2000-09-05
申请号：JP4751499
申请日：1999-02-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TERADA TOMOYUKI , NODA HIDEO , TSUBOI TOSHIHIRO , TANABE SHINICHI , KUNIMOTO YUKINORI , MORIMOTO TADAO , HORIUCHI MITSUAKI , SUNAKAWA KENJI , SATO TAKAYUKI
IPC分类号： A61B5/0492 , A61B5/0408 , A61B5/0478 , H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a high-performance microelectrode capable of detecting such problems as the breakage or severance of wire of through electrodes and wiring layers and to provide its manufacturing method. SOLUTION: This microelectrode provided with multiple wiring layers 6 has trouble detecting wiring layers 7 near the wiring layers 6. The manufacturing method of the microelectrode has a process for forming the trouble detecting wiring layers 7 near the wiring layers 6 concurrently with a process for forming the wiring layers 6 in the microelectrode having multiple wiring layers 6.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式