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1. 发明专利

JP2002057295A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002057295A
公开(公告)日：2002-02-22
申请号：JP2000245737
申请日：2000-08-14
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： IWASAKI TAKAYUKI , TAKEUCHI YUSUKE , YUYAMA YOSHIAKI , TANABE SHINICHI , SAKAI KOKI , NEMOTO MINEHIRO , NAMETAKE MASATAKE , KOJIMA YASUYUKI , WATANABE TOKUO , HORIUCHI MITSUAKI
IPC分类号： H01L21/76 , H01L21/762 , H01L21/822 , H01L21/84 , H01L23/52 , H01L23/522 , H01L27/04 , H01L27/12
摘要： PROBLEM TO BE SOLVED: To provide a technology to raise a resistant voltage of a semiconductor integrated circuit device formed on a so-called SOI substrate. SOLUTION: A circuit region 2 on the main surface of SOI substrate is connected to a separation region 9b partitioned with insulating separation trenches 4a and 4b using a wiring resistance or a diffusion resistance 11a in the SOI substrate. The separation region 9b is connected to an intermediate region 9 using the wiring resistance or a diffusion resistance 11b in the SOI substrate. Further, a circuit region 3 on the main surface of the SOI substrate is connected to a separation region 9c partitioned with insulating separation trenches 4c and 4d using the wiring resistance or a diffusion resistance 11d in the SOI substrate. The separation region 9c is connected to the intermediate region 9 using the wiring resistance or the diffusion resistance 11c in the SOI substrate. As a result, since a voltage applied between the circuit regions 2 and 3 is shared by the wiring resistance or the diffusion resistances 11a-11c, the resistant voltage of the semiconductor integrated circuit device is raised.

2. 发明专利

JP2000182985A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2000182985A
公开(公告)日：2000-06-30
申请号：JP36256098
申请日：1998-12-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： NODA HIDEO , TANABE SHINICHI , HORIUCHI MITSUAKI , KAWAGUCHI SHINJI
IPC分类号： H01L27/08 , H01L21/265 , H01L21/76 , H01L27/12 , H01L29/786
摘要： PROBLEM TO BE SOLVED: To improve performance and reliability of components of a wiring layer composed of a diffused layer, etc., by forming impurity ion implanted regions in contract with the surface of an insulation film on a part of semiconductor regions formed on an SOI substrate surface, and thermally diffusing the impurity in the impurity ion implanted regions. SOLUTION: On the surfaces of semiconductor regions 3 on an SOI substrate 4 an insulation film 5 of e.g. silicon oxide is formed, a resist film is formed on the insulation film 5, openings 7 are formed in the insulation film 5 by the lithography and the selective etching techniques, then the resist film is removed, an impurity ion is implanted in the semiconductor regions 3 underlying the openings 7 through the openings 7 of the insulation film 5 by the ion implanting method to form impurity ion implanted regions 8 in the semiconductor regions 3, so that the ion implanted regions 8 contact the surface of the insulation film 5, and the impurity is thermally diffused to form a diffused layer.

3. 发明专利

JP2001157669A MICROELECTRODE 失效
公开(公告)号：JP2001157669A
公开(公告)日：2001-06-12
申请号：JP34456199
申请日：1999-12-03
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TERADA TOMOYUKI , HORIUCHI MITSUAKI , TAZAWA MASAMITSU , NODA HIDEO , KUNIMOTO YUKINORI , TANABE SHINICHI , MORIMOTO TADAO , TSUBOI TOSHIHIRO , SUNAKAWA KENJI , SATO TAKAYUKI
IPC分类号： A61B5/0492 , A61B5/0408 , A61B5/0478 , A61B5/0488
摘要： PROBLEM TO BE SOLVED: To provide a microelectrode which permits signal treatment with a high S/N ratio and which has high performance and reliability. SOLUTION: A signal treatment circuit body 3 is electrically connected to the vicinity of a microelectrode body 2 via a wiring portion 4. In addition, the chip of the microelectrode body 2 and that of the signal treatment circuit body 3 are though to be a different chip or a chip of onchip structure.

4. 发明专利

JP2000197616A MANUFACTURE OF MICROELECTRODE 失效
公开(公告)号：JP2000197616A
公开(公告)日：2000-07-18
申请号：JP333999
申请日：1999-01-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： INOMAKI YOSHIHIRO , SAITO TOSHIO , KAWAGUCHI SHINJI , MORIYA SATOSHI , HORIUCHI MITSUAKI , TANABE SHINICHI , NODA HIDEO
IPC分类号： A61B5/0492 , A61B5/0408 , A61B5/0478 , G01N27/30 , H01L29/41
摘要： PROBLEM TO BE SOLVED: To provide a microelectrode manufacturing method capable of manufacturing an efficient microelectrode by making a simple manufacturing process. SOLUTION: The method has a process for etching a part of a semiconductor layer for forming an element and a part of an insulated film for an SOI on an SOI substrate, a process forming a semiconductor growing layer 4 on the surface of the SOI substrate by using an epitaxial growing device, a process for forming a wiring layer provided with a through electrode 6b and a pad 6a on the surface of an insulated film after forming the film on the surface of the layer 4 and a process for removing a semiconductor layer for a base being the rear surface of the microelectrode after then through the use of selective etching technique and then forming the supporting table 9 of the microelectrode by etching a part of the layer 1c and a part of the layer 4.

5. 发明专利

JP2000237155A MICROELECTRODE AND ITS MANUFACTURE 失效
公开(公告)号：JP2000237155A
公开(公告)日：2000-09-05
申请号：JP4751499
申请日：1999-02-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TERADA TOMOYUKI , NODA HIDEO , TSUBOI TOSHIHIRO , TANABE SHINICHI , KUNIMOTO YUKINORI , MORIMOTO TADAO , HORIUCHI MITSUAKI , SUNAKAWA KENJI , SATO TAKAYUKI
IPC分类号： A61B5/0492 , A61B5/0408 , A61B5/0478 , H01L21/3205 , H01L23/52
摘要： PROBLEM TO BE SOLVED: To provide a high-performance microelectrode capable of detecting such problems as the breakage or severance of wire of through electrodes and wiring layers and to provide its manufacturing method. SOLUTION: This microelectrode provided with multiple wiring layers 6 has trouble detecting wiring layers 7 near the wiring layers 6. The manufacturing method of the microelectrode has a process for forming the trouble detecting wiring layers 7 near the wiring layers 6 concurrently with a process for forming the wiring layers 6 in the microelectrode having multiple wiring layers 6.

6. 发明专利

JPH08250681A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08250681A
公开(公告)日：1996-09-27
申请号：JP6407496
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L29/78
摘要： PURPOSE: To flatten the surface of an interlayer insulating film by filling an interval between lower electrode layers with an interlayer insulating layer by making thicker the thickness of the interlayer insulating film than the specific amount of a distance between first electrodes of a memory cell where the first electrodes of the memory cell adjoin with a minimum interval. CONSTITUTION: This device comprises a plurality of word lines 27 that constitute a gate electrode 27 of a memory cell selecting MISFETQS, a first electrode 37 extending onto the word lines, and a second electrode 35 provided oppositely to the first electrode 37 through a dielectric 36. An interlayer insulating film 53 is provided between a second electrode 37 and a wiring 36. The first electrode 37 is independently of each memory cell M, and the second electrode 35 is formed commonly to a plurality of the memory cells. The interlayer insulating film 53 is constructed to be thicker than 1/2 of a distance between the first electrodes 37 where the first electrodes of the memory cell M adjoin with a minimum interval. Hereby, an interval between the lower layer electrode layers 35 is filled with the interlayer insulating film 53 to flatten the surface of the interlayer insulating film 53.

7. 发明专利

JPH08250601A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH08250601A
公开(公告)日：1996-09-27
申请号：JP6404696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8242 , H01L27/088 , H01L27/108 , H01L29/78
摘要： PURPOSE: To improve hot carrier withstand voltage by making virtually equal the dimensions in the direction of gate length of the semiconductor regions of low impurity concentration, which form the LDD structure of a first and a second MISFETs, respectively. CONSTITUTION: The n-channel MISFETs Qn of an input/output stage circuit and an internal circuit are composed of a gate insulating film 26, a gate electrode 27, a n-type semiconductor region 29, and a n--type semiconductor region 32, respectively. The side wall spacers 31 of these n-channel MISFETs Qn are virtually the same in size in the direction of gate length. The gate length of the n-channel MISFET Qn in the input/output stage circuit is made larger than that of the n-channel MISFET Qn in the internal circuit. Further, the n-type semiconductor regions 29 forming the LDD structure of the n-channel MISFETs are virtually the same in size in the direction of gate length. This improves hot carrier withstand voltage, and reduces threshold voltage drop with a lapse of time, which enables the improvement of electrical characteristics.

8. 发明专利

JPH08241969A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH08241969A
公开(公告)日：1996-09-17
申请号：JP6407696
申请日：1996-03-21
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： H01L21/768 , H01L21/3205 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/78
摘要： PURPOSE: To obtain a semiconductor integrated circuit device which enhances the moisture-proof of a passivation film formed on an interconnection layer by a method wherein the film thickness of an insulating film formed on an aluminum interconnection is specified by using a CVD method in which tetraethoxysilane is used as a source gas. CONSTITUTION: A passivation film 56 is formed on interconnections 55 which are composed mainly of aluminum alloy films 55B. The passivation film 56 is constituted of a composite film in which each of a silicon oxide film 56A deposited by a C-CVD method by using tetraethoxysilane as a source gas and a silicon nitride film 56B deposited by a plasma CVD method have been laminated in order. The silicon oxide film 56A at the lower layer of the passivation film 56 is constituted at a film thickness at 1/2 or higher of the interval between the interconnections 55 in regions in which the aspect ratio of the interval between the interconnections 55 to the film thickness of the interconnections 55 is at 1 or higher. By this constitution, the silicon oxide film 56A can be deposited at high step coverage at a low temperature at which the aluminum alloy films 55B for the interconnections 55 are not melted.

9. 发明专利

JPH07335750A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH07335750A
公开(公告)日：1995-12-22
申请号：JP13010494
申请日：1994-06-13
申请人： HITACHI LTD
发明人： YASUKAWA AKIO , KAWAJI MOTONORI , HORIUCHI MITSUAKI
IPC分类号： H01L23/522 , H01L21/768
摘要： PURPOSE:To prevent disconnection due to the growth of voids in a connecting section connecting a lower layer wiring and an upper layer wiring by forming a cavity section into an insulating layer brought near to the connecting section. CONSTITUTION:A lower layer wiring 2 and an upper layer wiring 8 are connected electrically through a through-hole connecting section 7, and buried into an insulating layer 1 and an insulating layer 9. A metal having low electric resistance is proper as the lower layer wiring 2 and the upper layer wiring 8 and a material having excellent insulating characteristics as the insulating layer 1 and the insulating layer 9. Cavity sections 5 are formed into insulating layers 3, 4, 6 brought near to the connecting section 7 particularly in the connecting section of the lower layer wiring 2 and the upper layer wiring 8. The cavity sections 5 surrounding the connecting section 7 is formed into the insulating layers 3, 4, 6 surrounding the connecting section 7. Accordingly, the rigidity of the insulating layer 3, 4, 6 sections brought near to the cavities 5 is reduced, the heat shrinkage of the wirings as the elastic deformation of the insulating layers 3, 4, 6 is absorbed, and growth of voids in the connecting section 7 is inhibited, thus preventing disconnection.

10. 发明专利

JPH0316153A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF AND APPARATUS FOR PRODUCTION THEREOF 失效
公开(公告)号：JPH0316153A
公开(公告)日：1991-01-24
申请号：JP6584989
申请日：1989-03-20
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SUGIURA JUN , TSUCHIYA OSAMU , OGASAWARA MAKOTO , OTSUKA FUMIO , TORII KAZUNARI , ASANO ISAMU , OWADA NOBUO , HORIUCHI MITSUAKI , TAMARU TAKESHI , AOKI HIDEO , OTSUKA NOBUHIRO , SHIRAI SEIICHIRO , SAGAWA MASAKAZU , IKEDA YOSHIHIRO , KAGA TORU , TSUNEOKA MASATOSHI , NIINA TOMOJI , OGISHI HIDEJI , KASAHARA OSAMU , ENAMI HIROMITSU , WAKAHARA ATSUSHI , AKIMORI HIROYUKI , SUZUKI SHINICHI , FUNATSU YOSHIAKI , KAWASAKI YOSHINAO , TSUBONE TSUNEHIKO , KOGANO MASAYOSHI , TSUGANE MASARU
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78
摘要： PURPOSE:To enhance an integration density by a method wherein a channel stopper region is formed in a main-face part under an insulating film for interelement isolation use of a substrate. CONSTITUTION:An oxidation-resistant mask whose film thickness is thin as compared with an oxidation-resistant mask of a first mask and an etching mask are laminated one after another; thereby, a second mask is formed. An etching treatment of a main face in an inert region of a substrate is executed by using the first and second masks; a groove is formed in the inert region of the substrate. Then, an oxidation treatment is executed by using the first and second masks; an insulating film for interelement isolation use (field insulating film) is formed on the main face of the inert region of the substrate. Then, the first and second masks are removed; after that, impurities are introduced into the whole main-face part including an active region and the inert region of the substrate; a channel stopper region is formed on the main-face part under the insulating film for interelement isolation use of the substrate. Thereby, an integration density can be enhanced.

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