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1. 发明专利

JPH02187997A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02187997A
公开(公告)日：1990-07-24
申请号：JP728089
申请日：1989-01-16
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： WADA MASASHI , MATSUO AKINORI , SHOJI KAZUYOSHI , IGUCHI MARIKO , KUBOTA YASURO , MUTO TADASHI , TAKAGI HITOSHI
IPC分类号： G11C17/00 , G11C16/06 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L29/788 , H01L29/792
摘要： PURPOSE:To contrive a high integration and the simplification of a breakdown strength protection of an element by outputting selectively two voltages from a drain by using two MOSFETs. CONSTITUTION:When a control signal C2 is set to such a low level as a ground potential, a P channel MOSFET Q24 is turned on, a power source terminal Vcc side works as a source, an output side VC1 side works as a drain, and the voltage Vcc can be outputted without losing a level. A MOSFET Q23 becomes an OFF state, when a control signal C1 to a gate is set to such a high level as a high voltage Vpp. Accordingly, the signal C1 of the FET Q23 becomes such a high level as the voltage Vpp and such a low level as '0'V, and such a boosting circuit as an N channel MOSFET is used becomes unnecessary. In such a way, and also, since no high level exists, a high integration can be executed and a dielectric strength breakdown preventing countermeasure of an element can be simplified.

2. 发明专利

JPS60157776A DETECTION FOR CODE ERROR 失效
公开(公告)号：JPS60157776A
公开(公告)日：1985-08-19
申请号：JP1197484
申请日：1984-01-27
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： MITA SEIICHI , IZUMIDA MORIJI , UMEMOTO MASUO , SHIONO HIROSHI , TAKAGI HITOSHI , ROKUTA MORIHITO
IPC分类号： G11B20/18 , H04N5/92
摘要： PURPOSE:To detect and correct code errors with a high precision without increasing the number of redundant bits by utilizing not only correlations of picture signals but also analog information of reproduced waveforms. CONSTITUTION:A reproduced analog waveform is converted to 2-bit digital information by an AD converter 1. Synchronizing data is reproduced by a synchronous detector 2 in accordance with the code of the MSB (corresponding to data discriminated as normal binary) of this information. This data is used to divide picture data to word units, and weights of individual data are detected by a weight detector 3. Weights of n-number of words obtained successively are added by an adder 4. The added weight is delayed by delay circuits (DL) 5 and 6, and weights of n-word units are compared. The MSB and the next bit are added by an EX-OR circuit 9, and coincidence between the output of the circuit 9 and the output of the comparator 7 is detected by an AND circuit 8. Output data of this AND circuit 8 and data whose timings of the MSBs are arranged by a delay circuit 10 are added by an EX-OR circuit 13 to obtain data where code errors are corrected.

3. 发明专利

JPS60668A DIGITAL SIGNAL RECORDING CIRCUIT 失效
公开(公告)号：JPS60668A
公开(公告)日：1985-01-05
申请号：JP10788383
申请日：1983-06-17
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： ROKUTA MORIHITO , MITA SEIICHI , IZUMIDA MORIJI , KOUNOUE AKIHIKO , FUJIMURA NOBUROU , TAKAGI HITOSHI , SHIONO HIROSHI , KANEDA HIDEHIRO
IPC分类号： G11B20/14
摘要： PURPOSE:To constitute a code with less consecutive ''0'' and without a DC component by providing a block conversion so as to reduce the consecutive ''0'' or ''1'' and adding a redundancy so as to eliminate the DC component and low frequency component. CONSTITUTION:Suppose that a data D1 in 16-bit is inputted to a serial parallel converting circuit 210, the data of first 8-bit in 16 bits is subject to NRZI conversion by using ''0'' as a redundancy bit at an ROM converting circuit 211 and the data 9-bit and the 4-bit binary-coding the weight information of the data is outoutped. Further, the data in latter 8-bit is processed similarly in an ROM converting circuit 212. The weight 4-bit outputted from the two ROM converting circuits 211 and 212 is added at a weight adder 214 and the outputted data becomes the weight 5-bit to the input data 16-bit. The weight 5-bit of the converted data and a DSV 5-bit are added at a weight accumulating value operating circuit 215 and when the inverting information is outputted, the waveform of E1 is inverted into the waveform of E2 so as to form a final data.

4. 发明专利

JPS59144014A Waveform equarizing system of magnetic recording or reproducing system 失效
标题翻译：磁记录或复制系统的波形均衡系统
公开(公告)号：JPS59144014A
公开(公告)日：1984-08-17
申请号：JP1754883
申请日：1983-02-07
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： MITA SEIICHI , IZUMIDA MORIJI , KOUNOUE AKIHIKO , FUJIMURA NOBUROU , TAKAGI HITOSHI
IPC分类号： H04B3/06 , G11B20/10 , G11B20/16 , H04L25/03
CPC分类号： G11B20/10009
摘要： PURPOSE:To improve greatly the code error factor by equalizing selectively the wave to be interfered and making use of a fact that a waveform having large interference between codes and a normal waveform within the original allowable value are mixed into a time variance component in terms of time. CONSTITUTION:Waveform compensating circuits 2 and 4 use transversal filters containing delay lines 6 and 7 or 17 and 18, attenuators 8 and 9 or 19 and 20, and an adder 10 or 21. The amount of compensation of the frequency characteristics is decided from the amounts of delay and addition. An amplitude controller 3 consists of buffer amplifiers 12 and 13, diodes 14 and 15, and attenuators 11 and 16. A variable attenuator 11 controls the amplitude applied to a pair of diodes, and therefore the threshold level can be set freely. For instance, the output voltage of the amplifier 12 is set at 2V and therefore it is possible to give compensation to a signal having the total reduction of amplitude by 6dB as long as a Schottky diode is used. As a result, the code error factor can be greatly improved.
摘要翻译：目的：通过选择性地平衡待干扰的波并利用以下事实来改善代码误差因子：使代码之间的干扰大，原始允许值内的正常波形的波形被混合成时间方差分量时间。构成：波形补偿电路2和4使用包含延迟线6和7或17和18，衰减器8和9或19和20以及加法器10或21的横向滤波器。频率特性的补偿量由延迟和增加的数量。振幅控制器3包括缓冲放大器12和13，二极管14和15以及衰减器11和16.可变衰减器11控制施加到一对二极管上的振幅，因此可以自由设定阈值电平。例如，放大器12的输出电压设定为2V，因此只要使用肖特基二极管，就可以对振幅总减小6dB的信号进行补偿。结果，代码误差因子可以大大提高。

5. 发明专利

JPH0562490B2 失效
公开(公告)号：JPH0562490B2
公开(公告)日：1993-09-08
申请号：JP11948784
申请日：1984-06-11
申请人： HITACHI LTD , HITACHI ELECTRONICS , HITACHI VIDEO ENG
发明人： MITA SEIICHI , IZUMIDA MORIJI , MICHIKAWA JUICHI , KATAYAMA HITOSHI , SHIONO HIROSHI , TAKAGI HITOSHI , ROKUTA MORIHITO , DOI NOBUKAZU
IPC分类号： G11B20/10 , H03K5/01
摘要： An apparatus for regenerating original signals comprising: means for introducing a first signal that is produced as an original signal passes through a system that cuts off predetermined frequencies; a first circuit means 30 which produces a third signal obtained on an open loop responsive to said first signal and a second signal which is regenerated from a signal of a predetermined frequency that is cut off by said system; and a second circuit means 12 which regenerates the original signal by converting said third signal into a binary signal.

6. 发明专利

JPH04332901A MAGNETIC RECORDING AND REPRODUCING SYSTEM 失效
公开(公告)号：JPH04332901A
公开(公告)日：1992-11-19
申请号：JP12817691
申请日：1991-05-02
申请人： HITACHI LTD
发明人： USHIKUBO TORIO , TAKAGI HITOSHI
IPC分类号： G11B5/027 , G11B15/02 , G11B27/02
摘要： PURPOSE:To provide a system which can be connected easily and surely and which can be operated conveniently in the system which performs a dubbing operation by using two VTR's. CONSTITUTION:Input/output ports 1, 2, 6, 7, 10, 11 of control signals, video signals and audio signals from individual VTR's 15 are changed over and connected alternatively according to a recording/replay mode by means of corresponding terminals 4, 9, 13 for external connection use and respective changeover switches 3, 8, 12. Corresponding terminals out of the terminals 4, 9, 13 for external connection use of the two VTR's are connected collectively by using one coaxial multicore cable 14.

7. 发明专利

JPS60191476A Reproducing circuit for digital signal 失效
标题翻译：数字信号再生电路
公开(公告)号：JPS60191476A
公开(公告)日：1985-09-28
申请号：JP4547084
申请日：1984-03-12
申请人： Hitachi Ltd , Hitachi Video Eng Co Ltd
发明人： SHIONO HIROSHI , IZUMIDA MORIJI , MITA SEIICHI , UMEMOTO MASUO , TAKAGI HITOSHI
IPC分类号： G11B20/10 , G11B20/14 , H04N5/92
CPC分类号： G11B20/10527 , G11B20/14
摘要： PURPOSE:To reduce the scale of a digital signal reproducing circuit by outputting the word weight of data after 8-8 conversion in the form of an eight-level analog voltage value corresponding to the number of ''1''s in one word of reproduced data. CONSTITUTION:A video signal is supplied to an A/D converter 2 through an input terminal 1, sampled with a clock of about 10 MHz and then converted into an eight-bit digital signal as the 1st data; and this 1st data is converted by a converter 3 according to an 8-8 conversion rule to output the 2nd data. Further, an inverting circuit 4 the 2nd data as it is as odd-numbered data and converts even-numbered words into the 3rd data wherein ''1'' and ''0'' are inverted, and this 3rd data is supplied to a converter 5, which converts the 8-bit parallel data into serial data. A synchronizing data adding circuit 6 adds synchronizing data and the resulting data is recorded on a magnetic tape 8. Reproduced serial data is inputted to a synchronizing data detecting circuit 9 during reproduction to generate an inverted pulse B. Further, the reproduced data A is supplied to a simple demodulating circuit 10 to obtain an analog level output 11. Consequently, the digital data is reproduced as the 8-level analog signal.
摘要翻译：目的：为了减少数字信号再生电路的规模，通过输出8-8转换后的数据的字重量，以八位模拟电压值的形式对应于一个字中的“1”数再现数据。构成：通过输入端子1将视频信号提供给A / D转换器2，以约10MHz的时钟采样，然后转换为8位数字信号作为第一数据; 并且该第一数据由转换器3根据8-8转换规则转换以输出第二数据。此外，反相电路4将第二数据原样作为奇数数据，并将偶数字转换成其中“1”和“0”的第三数据被反转，并将该第三数据提供给转换器5，其将8位并行数据转换为串行数据。同步数据添加电路6添加同步数据，并将得到的数据记录在磁带8上。在再现期间，将再现的串行数据输入到同步数据检测电路9，以产生反相脉冲B.此外，再现数据A被提供到简单的解调电路10以获得模拟电平输出11.因此，数字数据被再现为8电平模拟信号。

8. 发明专利

JPS60667A DIGITAL SIGNAL MODULATING SYSTEM 失效
公开(公告)号：JPS60667A
公开(公告)日：1985-01-05
申请号：JP10788283
申请日：1983-06-17
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , TAKAGI HITOSHI , ROKUTA MORIHITO , KANEDA HIDEHIRO , FUJIMURA NOBUAKI , SHIONO HIROSHI
IPC分类号： H03M7/00 , G11B20/14
摘要： PURPOSE:To limit the consecution of a same code and also to eliminate a DC and a low frequency component by adding a slight redundancy bit in a circuit converting a data of input (2n-1)-bit into a data in 2n-bit. CONSTITUTION:The conversion of 7-bits into 8-bits is exemplified. In fig., 1 is a serial parallel converting circuit, 2 is read only memory ROM storing a conversion table, 3 is a parallel serial conversion circuit and 4 is a DSV calculating circuit. An input data is converted into a parallel data P (7-bit) by the serial parallel converting circuit 1 and this data is inputted to the ROM 2. Further, a data S representing the pluse or minus sign of an accumulated value DSV of the weight of past data is inputted to this ROM. The converted data Q and the weight R of the data are calculated and outputted based on 8 data. The converted data q is inputted to the parallel serial converting circuit 3, where the data is outputted after being converted into a serial data.

9. 发明专利

JPS59186106A Digital signal recording circuit 失效
标题翻译：数字信号记录电路
公开(公告)号：JPS59186106A
公开(公告)日：1984-10-22
申请号：JP6084283
申请日：1983-04-08
申请人： Hitachi Denshi Ltd , Hitachi Ltd
发明人： IZUMIDA MORIJI , MITA SEIICHI , KOUNOUE AKIHIKO , TAKAGI HITOSHI , ROKUTA MORIHITO , SHIONO HIROSHI , KANEDA HIDEHIRO
IPC分类号： G11B20/14 , G11B20/10
CPC分类号： G11B20/10203
摘要： PURPOSE:To suppress an average DC component without prolonging consecution of 0 or 1 by adding a redundancy bit to decrease the consecution of 0 or 1 and a redundancy bit to eliminate a DC component so as to decrease the rate of rise of a data rate. CONSTITUTION:An NRZ signal is converted into an NRZI signal so as to prevent the expansion of error due to blocking. The 1st modulation circuit 20 adds the 1st redundancy bit and controls the block so that 1s share over a half of the block. The 2nd modulation circuit 30 adds the 2nd redundancy bit and controls the block so that the accumulative value of weight closes to 0. The NRZI data is a code where preceding and succeeding bits are related to each other and two degrees of freedom are given by inserting two redundancy bits between blocks. Thus, the DC component is eliminated by using comparatively less number of redundancy bits and further, the consecution of 1s and 0s is decreased.
摘要翻译：目的：通过添加冗余位来减少0或1的连续性来抑制平均直流分量，而不延长连续使用0或1，并且冗余位消除直流分量，以降低数据速率的上升率。构成：NRZ信号被转换成NRZI信号，以防止由于阻塞造成的误差扩大。第一调制电路20添加第一冗余位并控制块，使得1s共享该块的一半以上。第二调制电路30加上第二冗余位，并控制块，使得重量的累计值接近0. NRZI数据是前后位彼此相关的代码，并且通过插入来给出两个自由度块之间的两个冗余位。因此，通过使用相对较少数量的冗余位来消除DC分量，并且还减少了1s和0s的连续性。

10. 发明专利

JPS6376586A VIDEO TAPE RECORDER WITH AV CONTROL 失效
公开(公告)号：JPS6376586A
公开(公告)日：1988-04-06
申请号：JP21932186
申请日：1986-09-19
申请人： HITACHI LTD
发明人： OTSUKA SUSUMU , TAKAGI HITOSHI
IPC分类号： H04N5/44 , H04N5/765 , H04N5/91
摘要： PURPOSE:To exactly supply an antenna input RF signal from the VTR-side to the TV-side by providing the titled recorder with a switch function to detect the inputting or an AV control signal to an AV control terminal. CONSTITUTION:The terminal of the switch 1' of the Av control terminal 1, is connected to the base of a transistor 3; a control signal is supplied to a control circuit 4 from the emitter of the transistor 3 through resistors 2, 2'. Accordingly in case a connection pin is not inserted in the AV control terminal 1, the emitter of the transistor 3 is at a level L, and no control signals are supplied to the control circuit 4. When a connection pin is inserted, the emitter of the transistor 3 turns to a level H, and a control signal is supplied to the control circuit 4. The change-over switch 7 turns to a connecting point (a) side when the connection pin is inserted in the AV control terminal 1, but to a connecting point (b) side when not inserted.

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