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1. 发明专利

JPS60163280A MODULATING SYSTEM OF DIGITAL SIGNAL 失效
公开(公告)号：JPS60163280A
公开(公告)日：1985-08-26
申请号：JP1522784
申请日：1984-02-01
申请人： HITACHI LTD , HITACHI ELECTRONICS , HITACHI VIDEO ENG
发明人： ROKUTA MORIHITO , MITA SEIICHI , IZUMIDA MORIJI , KANEDA HIDEHIRO , SHIONO HIROSHI
IPC分类号： H03M5/06 , G11B20/14 , G11B20/16 , H03M7/14 , H04L25/49
摘要： PURPOSE:To reduce a clock rate less than a 3PM code, to increase the width of a detecting window and to suppress or remove a DC component or a low frequency component by converting an input signal into a code word inserting one or more ''0''s between ''1'' and ''1'' to attain NRZI conversion. CONSTITUTION:An inputted NRZ signal is divided for every M (positive integer) bits and the M bits are converted into a code word consisting of N (M

2. 发明专利

JPH0562490B2 失效
公开(公告)号：JPH0562490B2
公开(公告)日：1993-09-08
申请号：JP11948784
申请日：1984-06-11
申请人： HITACHI LTD , HITACHI ELECTRONICS , HITACHI VIDEO ENG
发明人： MITA SEIICHI , IZUMIDA MORIJI , MICHIKAWA JUICHI , KATAYAMA HITOSHI , SHIONO HIROSHI , TAKAGI HITOSHI , ROKUTA MORIHITO , DOI NOBUKAZU
IPC分类号： G11B20/10 , H03K5/01
摘要： An apparatus for regenerating original signals comprising: means for introducing a first signal that is produced as an original signal passes through a system that cuts off predetermined frequencies; a first circuit means 30 which produces a third signal obtained on an open loop responsive to said first signal and a second signal which is regenerated from a signal of a predetermined frequency that is cut off by said system; and a second circuit means 12 which regenerates the original signal by converting said third signal into a binary signal.

3. 发明专利

JPS60263512A WAVEFORM COMPENSATING SYSTEM 失效
公开(公告)号：JPS60263512A
公开(公告)日：1985-12-27
申请号：JP11948784
申请日：1984-06-11
申请人： HITACHI LTD , HITACHI ELECTRONICS , HITACHI VIDEO ENG
发明人： MITA SEIICHI , IZUMIDA MORIJI , MICHIKAWA YUUICHI , KATAYAMA HITOSHI , SHIONO HIROSHI , TAKAGI HITOSHI , ROKUTA MORIHITO , DOI NOBUNORI
IPC分类号： G11B20/10 , H03K5/01
摘要： PURPOSE:To compensate the waveform degradation, which is generated in a recording/reproducing system or a transmission system, to an optimum value by processing a digital signal, where the intercode interference is generated by frequency break, with an open loop. CONSTITUTION:When the digital signal where the intercode interference is generated is inputted, a discriminating circuit 12 discriminates it as ''1'' or ''0'', and required frequency components are extracted through a band pass filter 4. Meanwhile, a delay circuit 6 is so adjusted that transmission times of two routes to an adder 9 are equalized, and only frequency components which have complementary relations to those passing the filter 4 are allowed to pass a filter 5, and both of frequency components are applied to the adder 9. The output of the adder 9 is equal to the original recording or reproduced signal or transmission signal by relations of Q(f)+P(f)=1. Thereafter, a discriminating circuit 13 discriminates it as ''1'' or ''0'', and the signal is outputted. The waveform degradation is compensated to an optimum value because the digital signal is processed with the open loop in this manner.

4. 发明专利

JPS61248269A METHOD FOR TRANSMITTING DIGITAL SIGNAL AND ITS PROCESSOR 失效
公开(公告)号：JPS61248269A
公开(公告)日：1986-11-05
申请号：JP8861885
申请日：1985-04-26
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： IZUMIDA MORIJI , MITA SEIICHI , DOI NOBUKAZU , ROKUTA MORIHITO , SHIONO HIROSHI , KANEKO MAMORU , INUI FUYUKI
IPC分类号： G11B20/18 , G11B20/10 , H04L1/00
摘要： PURPOSE:To improve the reliability of a transmission signal between recording and reproducing devices for a digital signal at the transmission of the signal by transmitting the output of a reproducing signal processing means through a recording signal processing means in an equipment on a transmitting side, and receiving the transmitted signal by a recording signal processing means through a reproducing signal processing means in the equipment on a receiving side. CONSTITUTION:Digital data 6a detected and corrected by a reproducing signal processing circuit 11a are inputted to a recording signal processing circuit 12a to add an additional signal such as an error correcting parity and a synchronizing pattern to the input signal 6a and the added signal is outputted to a reproducing signal processing circuit 11b on the recording side. The circuit 11b detects and corrects an error generated in a transmission line A at the time of transmission from a digital VTR 10a to a VTR 10b and outputs the corrected signal to a recording signal processing circuit 12b as an original digital signal 7b. The circuit 12b adds an additional signal such as an error correcting parity and a synchronizing pattern to the digital signal 7b sent from the circuit 11b and outputs the added signal to a magnetic recording/reproducing device 13b. The device 13 records a signal 8b outputted from the circuit 12b in a recording medium.

5. 发明专利

JPS61242424A ERROR CORRECTING METHOD 失效
公开(公告)号：JPS61242424A
公开(公告)日：1986-10-28
申请号：JP8431985
申请日：1985-04-19
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： IZUMIDA MORIJI , DOI NOBUKAZU , MITA SEIICHI , SAITO AKIRA , ROKUTA MORIHITO , SHIONO HIROSHI
IPC分类号： H03M13/00
摘要： PURPOSE:To correct occurring errors and to reduce missing by adding the 1st pointer to an uncorrectable word when decoding is performed at an initial state and adding the 2nd pointer to some of uncorrectable words without error correction when an error in one word is a pattern other then a specific pattern. CONSTITUTION:A data sequence 100 inputted to an input terminal 10 is supplied to a syndrome arithmetic circuit 210 to calculate syndromes S0, S1, S2, and S3. For example, the syndrome S0 is obtained by EORing (exclusively ORing) data 00,01...08, and 09 with words having parity data B00, B01, B02, and B03 and constituted a one-byte (8-bit) signal. Those four syndromes S0, S1, S2, and S3 (201) are outputted to an error position and error pattern arithmetic circuit 220. The error position and error pattern arithmetic circuit 220 calculates an error occurrence position and an error pattern from the syndromes S0, S1, S2, and S3.

6. 发明专利

JPS61269532A PHASE LOCKED LOOP CIRCUIT 失效
公开(公告)号：JPS61269532A
公开(公告)日：1986-11-28
申请号：JP11043785
申请日：1985-05-24
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： IZUMIDA MORIJI , DOI NOBUKAZU , MITA SEIICHI , ROKUTA MORIHITO , SHIONO HIROSHI
IPC分类号： H03L7/14 , H03L7/06 , H04L7/033 , H04N5/93
摘要： PURPOSE:To obtain a voltage controlled oscillation output signal with less affected by dropout by switching an input signal during dropout period into an output signal in a phase locked loop control circuit to which a discontinuous signal is inputted due to dropout. CONSTITUTION:A selector circuit 10 selecting the output of a tank circuit 2 and an output of a voltage controlled oscillation circuit 6 is added. The circuit 10 is phase-locked in loop by an output of an envelope detection circuit 7, the output of the circuit 2 while no dropout exists selects the output of the circuit 16 when dropout takes place. An output 11 of the circuit 10 and an output 12 of the circuit 6 input to a phase comparator 3 to generate an error voltage 13 proportional to the phase difference, after the voltage is smoothed by an LPF 5, the result is inputted to the circuit 6. The circuit 6 outputs a signal 12 having a frequency proportional to the input voltage 14 and feeds back it to the circuit 10 and the comparator 3.

7. 发明专利

JPS60157776A DETECTION FOR CODE ERROR 失效
公开(公告)号：JPS60157776A
公开(公告)日：1985-08-19
申请号：JP1197484
申请日：1984-01-27
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： MITA SEIICHI , IZUMIDA MORIJI , UMEMOTO MASUO , SHIONO HIROSHI , TAKAGI HITOSHI , ROKUTA MORIHITO
IPC分类号： G11B20/18 , H04N5/92
摘要： PURPOSE:To detect and correct code errors with a high precision without increasing the number of redundant bits by utilizing not only correlations of picture signals but also analog information of reproduced waveforms. CONSTITUTION:A reproduced analog waveform is converted to 2-bit digital information by an AD converter 1. Synchronizing data is reproduced by a synchronous detector 2 in accordance with the code of the MSB (corresponding to data discriminated as normal binary) of this information. This data is used to divide picture data to word units, and weights of individual data are detected by a weight detector 3. Weights of n-number of words obtained successively are added by an adder 4. The added weight is delayed by delay circuits (DL) 5 and 6, and weights of n-word units are compared. The MSB and the next bit are added by an EX-OR circuit 9, and coincidence between the output of the circuit 9 and the output of the comparator 7 is detected by an AND circuit 8. Output data of this AND circuit 8 and data whose timings of the MSBs are arranged by a delay circuit 10 are added by an EX-OR circuit 13 to obtain data where code errors are corrected.

8. 发明专利

JPH01320874A SPECIAL PICTURE DEVICE 失效
公开(公告)号：JPH01320874A
公开(公告)日：1989-12-26
申请号：JP15231888
申请日：1988-06-22
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： ABE MASAHIRO , SUINA FUMIO , ROKUTA MORIHITO
IPC分类号： H04N5/265 , H04N5/45
摘要： PURPOSE:To stably synthesize pictures by clamping a second video signal with its DC voltage part at the time of synthesizing the second reduced video signal with a first video signal. CONSTITUTION:The first video signal is given from input terminal 1 to a picture synthesizing switch 15 through a peak clamp circuit 13. The second reduced video signal is given to a keyed clamp circuit 31. A keyed clamp pulse 32 corresponding to the DC voltage part of the second video signal is supplied to the keyed clamp circuit 31 from a control circuit 16. The picture synthesizing switch 15 is switched by the control circuit 16 to synthesize first and second video signals.

9. 发明专利

JPH01300683A SPECIAL PICTURE DEVICE 失效
公开(公告)号：JPH01300683A
公开(公告)日：1989-12-05
申请号：JP13031188
申请日：1988-05-30
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SUZUKI HIROAKI , ABE MASAHIRO , FUKUDA HIROKI , SHIINA FUMIO , ROKUTA MORIHITO
IPC分类号： H04N5/265 , H04N9/74
摘要： PURPOSE:To attain synthesis of patterns in a free form by generating a key signal based on a signal read out of a picture memory corresponding to the picture memory and written therein. CONSTITUTION:In the case of reading out the picture information written in the picture memory 3, a key signal for picture synthesis is generated based on a picture digital data or the information for picture synthesis is written in advance in the key signal memory 4 corresponding one to one to the address of the picture memory 3, it is read out of the memory 4 synchronously with the picture information to activate a changeover switch 6 for picture synthesis. Thus, the key signal is switched freely depending on the picture information. Then the synthesis of two picture or over is attained freely.

10. 发明专利

JPS60106074A DIGITAL MAGNETIC PICTURE RECORDER 失效
公开(公告)号：JPS60106074A
公开(公告)日：1985-06-11
申请号：JP21235383
申请日：1983-11-14
申请人： HITACHI LTD , HITACHI ELECTRONICS
发明人： UMEMOTO MASUO , MITA SEIICHI , IZUMIDA MORIJI , ROKUTA MORIHITO , MIYAZAKI SHINICHI
IPC分类号： G11B20/12 , G11B20/10 , H04N5/91 , H04N5/92
摘要： PURPOSE:To enhance equilibrium property of digital information to be recorded without a rise of a bit rate by converting and recording a digital information pattern of two samples into the digital pattern in which 1 and 0 is approximately balanced. CONSTITUTION:16 bits in a block are distributed to Channel 6 by a distributing circuit 4. In such a way a bit rate drops to one-sixth, and the bit rate becomes 70Mbit/sec, which can be used on a commercial basis. Since an output of the distributing circuit 4 is a parallel output of 16 bits, it is converted into a series output of 16 bits, it is converted into a series output by parallel/serial convertors 5-1-5-6 and the series output is recorded on a magnetic tape through heads 6-1-6-6. In order to reproduce, a reverse process of the recording is constituted. Since 16 bits/16 bits convertor 3 is of large capacity of 2 X16=1,048,576 bits, the convertor 3 cannot be constituted with one unit of ROM memory, and utilizes four units of the ROM memory with 65,536X4 bits (so called 256k bits).

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