会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明专利
    • PRINTED-WIRING BOARD
    • JPH10233572A
    • 1998-09-02
    • JP3737997
    • 1997-02-21
    • HITACHI LTDHITACHI VIDEO IND INF SYST INC
    • KOBAYASHI SHINJINAKANO YUJINAGIRI TOMOHARU
    • H05K3/34H05K3/12
    • PROBLEM TO BE SOLVED: To reduce the width direction of a solder paste and to suppress a bridge between adjacent soldering pads by a method wherein a silk-screen printed part is formed around surface mounting-type narrow-pitch IC pads on the board. SOLUTION: Surface mounting-type narrow-pitch IC pads 1 are provided, a silk-screen printed part 2 is formed on a resist 3 at the pads 1, a metal mask 5 is placed on a board 4, a solder paste 6 is moved in the direction of an arrow A by using a squeegee 7, and the solder paste 6 is supplied onto the IC pads from opening parts 8 in the metal mask 5. At this point, the thickness of the solder paste to be supplied is added to the thickness (d) of the metal mask 5, and the solder paste is supplied excessively by the difference (f) between the thickness portion (c) of a resist printed part plus the silk-screen printed part and the thickness (e) of the soldering pads 1. Thereby, the width direction of the solder paste can be reduced, and it is possible to prevent a solder bridge between the adjacent soldering pads 1.
    • 4. 发明专利
    • Convergence correction circuit and display device using it
    • 综合校正电路和使用它的显示设备
    • JP2004080609A
    • 2004-03-11
    • JP2002240647
    • 2002-08-21
    • Hitachi Ltd株式会社日立製作所
    • NAGIRI TOMOHARUYOSHIZAWA KAZUHIKOWATANABE TOSHIMITSUMATSUMI KUNINORI
    • H04N9/28
    • PROBLEM TO BE SOLVED: To reduce the cost of a convergence correction circuit by making a working memory unnecessary.
      SOLUTION: The convergence correction circuit is provided with a muting circuit which outputs the convergence correction data of each channel read out from a memory correspondingly to scanning by turning on/off the data, forms a correction waveform for each channel by independently controlling the muting circuit at every channel by means of a control means, such as the CPU etc., and forms a driving signal used for performing convergence correction based on the correction waveform. When the correction circuit corrects convergence correction data, the circuit temporarily stores intermediate corrected results in a memory of a color other than the color to be subjected to convergence adjustment.
      COPYRIGHT: (C)2004,JPO
    • 要解决的问题:通过不需要工作记忆来降低会聚校正电路的成本。 解决方案:会聚校正电路设置有静噪电路,其通过接通/关闭数据来输出从与存储器相对应的扫描读出的每个通道的会聚校正数据,通过独立控制形成每个通道的校正波形 通过诸如CPU等的控制装置在每个通道处的静噪电路,并且基于校正波形形成用于执行会聚校正的驱动信号。 当校正电路校正收敛校正数据时,电路将中间校正结果临时存储在不同于要进行会聚调整的颜色之外的颜色的存储器中。 版权所有(C)2004,JPO
    • 5. 发明专利
    • Digital convergence correction apparatus and display using the same
    • 数字整合校正装置和使用它的显示
    • JP2003009169A
    • 2003-01-10
    • JP2001185938
    • 2001-06-20
    • Hitachi Ltd株式会社日立製作所
    • MATSUMI KUNINORIYOSHIZAWA KAZUHIKOWATANABE TOSHIMITSUNAGIRI TOMOHARU
    • H04N9/28G09G1/10G09G1/28
    • PROBLEM TO BE SOLVED: To provide a digital convergence correction apparatus for reducing the disturbance in convergence waveforms being generated when a CPU operates a memory.
      SOLUTION: The digital convergence correction apparatus comprises a memory 13, an address generator 11 for generating a first address signal, a CPU 18 for generating a second address signal for reading/rewriting convergence correction data, an address switcher 12, a data switcher 14, and a latch 15 for retaining the convergence correction data. In the digital convergence correction apparatus, when the CPU 18 switches the address switcher 12 and the data switcher 14 to a terminal (b) to operate the memory 13 where convergence correction data are stored in convergence adjustment, the CPU 18 stops a latch pulse LP, and retains the immediately preceding convergence correction data in the latch 15.
      COPYRIGHT: (C)2003,JPO
    • 要解决的问题:提供一种用于减少当CPU操作存储器时产生的会聚波形的干扰的数字会聚校正装置。 解决方案:数字会聚校正装置包括存储器13,用于产生第一地址信号的地址发生器11,用于产生读/重写会聚校正数据的第二地址信号的CPU18,地址切换器12,数据切换器14, 以及用于保持会聚校正数据的锁存器15。 在数字会聚校正装置中,当CPU 18将地址切换器12和数据切换器14切换到终端(b)以操作收敛校正数据在会聚调整中的存储器13时,CPU 18停止锁存脉冲LP 并且将紧接在前的会聚校正数据保持在锁存器15中。