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1. 发明专利

JPH0211077A STILL PICTURE REPRODUCING CIRCUIT 失效
公开(公告)号：JPH0211077A
公开(公告)日：1990-01-16
申请号：JP15917988
申请日：1988-06-29
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： MATONO TAKAAKI , HIRAHATA SHIGERU , SUGIYAMA MASAHITO , KATSUMATA KENJI , SUZUKI SUNAO , KAIZAKI KAZUHIRO
IPC分类号： H04N7/08 , H04N5/907 , H04N5/937 , H04N7/081
摘要： PURPOSE:To reproduce a stable black level on a total digital basis by providing a switching circuit which switches a reference level in the blanking period of a video signal reproduced by a reference level reproducing circuit with a video signal read from a picture memory. CONSTITUTION:A reference level (black level) reproducing circuit 107 in the blanking period of the video signal extracts the reference level in the blanking period out of the video signal before writing into a picture memory 108 by a reference level extracting circuit 201, cumulatively adds them, and reproduces the reference level. A reference level holding circuit holds the reference level reproduced from the reference level reproducing circuit 107 in the still picture reproducing period. Further, a switching circuit 109 switches the blanking period of the video signal read from the picture memory 108 with the reference level reproduced from the reference level reproducing circuit 107. Thus, the stable black level can be correctly reproduced on the total digital basis.

2. 发明专利

JPH01212987A VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH01212987A
公开(公告)日：1989-08-25
申请号：JP3648388
申请日：1988-02-20
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： MATONO TAKAAKI , HIRAHATA SHIGERU , SUGIYAMA MASAHITO , KATSUMATA KENJI , SUZUKI SUNAO , TORIGOE SHINOBU , NAKAGAWA HIMIO , MIYAKE HIROMASA
IPC分类号： H04N7/01
摘要： PURPOSE:To prevent the number of output pins from being increased at the time of an LSI formation by selecting and outputting a signal for obtaining the video signal of 2:1 interlace and a signal for obtaining the video signal of 1:1 non-interlace according to an inputted video signal or a mounted television receiver or the like. CONSTITUTION:A synchronizing and separating circuit 110 separates a horizontal synchronizing signal fH and a vertical synchronizing signal fV and outputs from a composite color television signal. The horizontal synchronizing signal fH separated by the synchronizing and separating circuit 110 is inputted to a frequency converting circuit 111 and converted to the horizontal synchronizing signal 2 fH having a frequency twice as high as the previous one. Then, the horizontal synchronizing signals fH and 2fH are inputted to a selecting circuit 112. When the signal of a high level is inputted as a control signal to a control signal input terminals 116, while the signal of the high level is inputted, a switching signal inputted to a switching signal input terminal 117 is inputted to multiplex circuits 113-115 through a multiplex prohibiting circuit 119 to alternately switch the switches of the respective multiplex circuits 113-115.

3. 发明专利

JPH03177182A CLOCK GENERATOR 失效
公开(公告)号：JPH03177182A
公开(公告)日：1991-08-01
申请号：JP31530489
申请日：1989-12-06
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： KURITA TOSHIYUKI , NAKAGAKI NOBUFUMI , SEKIYA HIROSHI , MURATA TOSHINORI , KAIZAKI KAZUHIRO , MATONO TAKAAKI
IPC分类号： H04N5/05 , H04N5/06 , H04N5/12 , H04N9/44
摘要： PURPOSE:To attain high picture quality by driving a synchronizing signal generating means with a clock synchronously with a horizontal synchronizing signal included in a video signal and driving a signal processing means with a clock outputted from a selection means. CONSTITUTION:A line lock clock (clock generated synchronously with a horizontal synchronizing signal included in an inputted video signal) 103 is synchronized with a burst lock clock (clock generated synchronously with a color burst signal included in video signal) 105 only when the video signal is a standard signal. When a non-standard signal is inputted to a signal processing circuit 110, a line lock clock 103 is given to the circuit 110 and when a standard signal is inputted, the burst lock clock 105 or the line lock clock 103 synchronously with the burst lock clock 105 is given to the circuit 110 respectively. Thus, even when the standard signal is inputted or the non-standard signal is inputted to the signal processing circuit 110, high picture quality is attained.

4. 发明专利

JPH0229077A VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0229077A
公开(公告)日：1990-01-31
申请号：JP17799488
申请日：1988-07-19
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： MATONO TAKAAKI , HIRAHATA SHIGERU , SUGIYAMA MASAHITO , KATSUMATA KENJI , KAIZAKI KAZUHIRO , SUZUKI SUNAO
IPC分类号： H04N5/16
摘要： PURPOSE:To reproduce the reference level of a video signal correctly by applying arithmetic sum to a signal level in a period being a blanking period in a video signal before the storage of a memory and outputting the obtained level as a reference level. CONSTITUTION:A black level reproducing circuit 111b integrates a signal level for a prescribed period in the blanking period of a composite color television signal being an output of an A/D converter 105c, that is, applies arithmetic means, and the obtained level is outputted as a black level. Then a changeover switch 115c applies switching according to a blanking pulse BLK from a memory control circuit 128, outputs an output signal from a movement adaptive Y separation circuit 106 during the video period and outputs a black level outputted from a black level reproducing circuit 111b during the blanking period. As a result, even if the information in the blanking period is missing, the black level of a luminance signal Y is reproduced.

5. 发明专利

JPH01272270A REDUCTION DISPLAYING CIRCUIT FOR VIDEO SIGNAL 失效
公开(公告)号：JPH01272270A
公开(公告)日：1989-10-31
申请号：JP10032788
申请日：1988-04-25
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： KATSUMATA KENJI , HIRAHATA SHIGERU , SUGIYAMA MASAHITO , MATONO TAKAAKI , TORIGOE SHINOBU , SUZUKI SUNAO , MIYAKE HIROMASA
IPC分类号： H04N5/265 , H04N5/45 , H04N5/66 , H04N5/937
摘要： PURPOSE:To allow a child picture of an animation, as well, to correctly display a video by selecting one of the outputs in three buffer memories which store the output of a child picture sampling circuit to thin a video signal for the child picture. CONSTITUTION:The input video signals are thinned by a child picture sampling circuit 103, and they are written into one of three buffer memories 107-109. A first switching circuit 104 selects and displays one buffer memory whose output synchronization and field conform to each other out of the two buffer memories which are not under writing from the three buffer memories 107-109. Consequently, reading and writing do not compete in the child picture. Thus, the new memory is unnecessary to be written, and the correct child picture display can be executed.

6. 发明专利

JPS63267092A PICTURE SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS63267092A
公开(公告)日：1988-11-04
申请号：JP9985287
申请日：1987-04-24
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SUGIYAMA MASAHITO , HIRAHATA SHIGERU , KATSUMATA KENJI , MATONO TAKAAKI , MURATA TOSHINORI , NAKAGAWA HIMIO , SUZUKI SUNAO
IPC分类号： H04N9/74 , H04N9/78
摘要： PURPOSE:To remove a reflected interference without increasing the circuit scale in the small screen for a multiscreen and to obtain a high picture quality by integrally constituting a reducing processing circuit for a reduced screen with a luminance signal and chrominance signal separating circuit. CONSTITUTION:The reducing-line processing circuit for the screen is integrally constituted with the comb filter circuit for separating the luminance signal and chrominance signal of a color television signal. The reducing processing circuit uses a line memory 2 to execute a vertical processing, limit a vertical band, execute a horizontal processing by a filter 6 and limit a horizontal band. The line memory 2 is commonly used as the line memory in the comb-line filter circuit for separating the luminance signal and the chrominance signal and the filter 6 for limiting the horizontal band is commonly used as the horizontal band limiting filter for separating the luminance signal and the chrominance signal. Thereby, the small screen of the high picture quality from which the reflected interference is not generated can be realized by suppressing the increase of the circuit scale.

7. 发明专利

JPH03194873A PIN CONNECTOR 失效
公开(公告)号：JPH03194873A
公开(公告)日：1991-08-26
申请号：JP33135189
申请日：1989-12-22
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： ARIKAWA SHUNICHI , MATONO TAKAAKI
IPC分类号： H01R13/719
摘要： PURPOSE:To exhibit a restraint effect with respect to noise transmitted by the central electrode of a pin connector by disposing a magnetic core inside a pin jack of a pin connector, and arranging insulators adjacent to the core. CONSTITUTION:A magnetic core 5 is held in the housing 1 of a pin jack in such a manner that either one or both of the central electrode 11 of a pin plug and the central electrode 2 of the pin jack are inserted through the central hole of the magnetic core 5 with the pin plug inserted into the housing 1 of the pin jack. When the central electrode 11 of the pin plug is engaged with the central electrode 2 of the pin jack, the electrode 11 is disposed in front of an insulator 3 so as to be inserted into the magnetic core 5 held by another insulator 4, and consequently, an inductance is applied in series to both electrodes. The material, shape and dimension of the core are selected suitably. Therefore, any noise transmitted by the central electrode of the pin connector can be restrained.

8. 发明专利

JPH0214689A SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPH0214689A
公开(公告)日：1990-01-18
申请号：JP16253088
申请日：1988-07-01
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SUZUKI SUNAO , KATSUMATA KENJI , MATONO TAKAAKI , SUGIYAMA MASAHITO , HIRAHATA SHIGERU
IPC分类号： H04N7/08 , H04N7/081 , H04N11/20
摘要： PURPOSE:To reproduce a freeze picture without flicker by controlling a selection circuit so that a timing generating circuit applies different selection depending on an odd number field and an even number field at the freeze mode. CONSTITUTION:Selection circuits 117, 118 at the freeze mode use control signals S4, S5 to select the position (b) in the even field respectively to correct the relation of scanning line. In the color difference signal processing system, selection circuits 131,135 use control signals S8, S9 to select the position (b) respectively and selection circuits 130, 134 use control signals S6, S7 to select the position (a) in the odd filed respectively and to select the position (b) respectively. Thus, in the odd field, a signal with 1H delay and in the even field, a signal not retarded is given to double speed conversion circuits 132, 136 as the interpolation scanning line signal. Thus, even if the pattern is changing in the vertical direction, no line flicker is produced.

9. 发明专利

JPH01318491A MOVEMENT DETECTING CIRCUIT AND EDGE DETECTING CIRCUIT 失效
公开(公告)号：JPH01318491A
公开(公告)日：1989-12-22
申请号：JP15032688
申请日：1988-06-20
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SUGIYAMA MASAHITO , HIRAHATA SHIGERU , KATSUMATA KENJI , MATONO TAKAAKI , TORIGOE SHINOBU , SUZAKI TORU , OZAWA TOSHIMITSU , SUZUKI SUNAO , MIYAKE YOSHIMASA
IPC分类号： H04N11/00 , H04N9/77 , H04N9/78 , H04N11/04 , H04N11/20 , H04N11/24
摘要： PURPOSE:To prevent a still picture being erroneously detected as animation by controlling sensitivity in detecting a movement by the edge information of the picture. CONSTITUTION:An inter-frame difference signal obtained with a frame memory 3 and a subtracting circuit 27 is supplied to an LPF28, the influence of a chrominance signal is removed, and the movement information of the low frequency component of a luminance signal is obtained. The absolute value of the movement information is obtained by an absolute value circuit 28 and after that supplied to a movement converting circuit 30, and a dynamic signal is obtained. Thus, even for the still picture at the time of a large edge signal, it can be prevented that the still picture tends to be erroneously detected as the animation by controlling the sensitivity in detecting the movement according to the edge information of the picture.

10. 发明专利

JPS63267074A PICTURE SIGNAL PROCESSOR 失效
公开(公告)号：JPS63267074A
公开(公告)日：1988-11-04
申请号：JP9985187
申请日：1987-04-24
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： HIRAHATA SHIGERU , KATSUMATA KENJI , SUGIYAMA MASAHITO , MATONO TAKAAKI , MURATA TOSHINORI , KAIZAKI KAZUHIRO , SUZUKI SUNAO
IPC分类号： H04N5/74 , H04N5/265
摘要： PURPOSE:To recognize continuing moving picture information on a slave screen without the defect of still screen information by synthesizing and reading a video signal stored in the first area of a memory circuit and a video signal for a small screen stored in a second area. CONSTITUTION:A first memory control circuit stores a video signal digitized in an A/D converting circuit 7 in the first area of the memory circuit 8 to store a still picture. A second memory control circuit stores a band limited video signal for the slave screen in the second area except the first area of the memory circuit 8 by filter circuits 27-29 and at the time of reading, the video signal stored in the first area of the memory circuit 8 is synthesized with the video signal for the slave screen stored in the second area and read. Thereby, the still picture stored in the first area can be reproduced on the slave screen under a stored state without being destroyed according to the storage and the reproduction of the slave screen and the continuing moving picture information can be recognized on the still screen.

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