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1. 发明专利

JPH06191099A PRINT CONTROL SYSTEM 失效
公开(公告)号：JPH06191099A
公开(公告)日：1994-07-12
申请号：JP34379492
申请日：1992-12-24
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： WADA HIROSHI , WAKIZAKA SHINJI , HASEGAWA KAZUKO , SATO HIROKO , SHIRANE HIROAKI , NISHIMOTO KAZUHISA , KIRIYAMA NORIO , HAYASHI SHIGEO
IPC分类号： B41J5/30 , B41J29/38
摘要： PURPOSE:To print data for one page in a small memory capacity by providing two memories each having 1/4 the memory capacity necessary to represent one page, forming next data in the other memory during printing of the data formed in the one memory, and repeating it after the formation of the data and the printing are finished. CONSTITUTION:A CPU 1 forms data 21 in a page memory A. Then, printing of data of the memory A is started, and data 22 is formed in a page memory B. If any of the printing and the formation is not finished, it is weighted as it is. If the both are finished, printing of data of the memory B is started, and data 23 is formed in the memory A. If any of the printing and the formation is not finished, it is weighted as it is. If the both are finished, printing of the data of the memory A is started, and data 24 is formed in the memory B. Similarly, if both the printing and the formation are finished, printing of the data of the memory B is started. If the printing is finished, printing of one page is finished.

2. 发明专利

JPH06324666A CHARACTER GENERATING DEVICE 失效
公开(公告)号：JPH06324666A
公开(公告)日：1994-11-25
申请号：JP10906393
申请日：1993-05-11
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： WAKIZAKA SHINJI , HASEGAWA KAZUKO , WADA HIROSHI , SATO HIROKO , SHIRANE HIROAKI , NISHIMOTO KAZUHISA , HAYASHI SHIGEO
IPC分类号： G09G5/24 , G06T11/20 , G06F15/72
摘要： PURPOSE:To obtain a character generating device which is suitable to power consumption reduction of a system and LSI-implementation by composing the device of plural modules and stopping the functions of modules which do not operate in accordance with modes. CONSTITUTION:A module 1 (13) is a vector block and a module 2 (14) is a raster block. For example, when mode information written in a mode register 11 indicates a mode wherein the process of the vector block is not performed for outline font data inputted to the character generating device, a block supply control circuit 12 does not supply a clock CLK1 to the vector block. A necessary irreducible clock, however, is supplied for transfer from a font input FIFO to an FIFO through the vector block. A mode wherein the process of the raster block is not performed is the same. Thus, the functions of the modules 13 and 14 which do not operate to perform conversion specified by the modes are stopped.

3. 发明专利

JPH06161421A CHARACTER GENERATING DEVICE 失效
公开(公告)号：JPH06161421A
公开(公告)日：1994-06-07
申请号：JP30846892
申请日：1992-11-18
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： WAKIZAKA SHINJI , HASEGAWA KAZUKO , WADA HIROSHI , SATO HIROKO , SHIRANE HIROAKI , NISHIMOTO KAZUHISA , HAYASHI SHIGEO , KIRIYAMA NORIO
IPC分类号： G09G5/24 , G06T11/20 , G06F15/72
摘要： PURPOSE:To obtain the best processing speed of a system and to improve character quality by providing a raster block which reads dot data in, paints out the inside of the outline of a character, and stored the resulting data in a dot memory again. CONSTITUTION:This character generating device is equipped with a CPU interface 2, a front input FIFO 3 which temporarily stores outline font data from a font memory, and a vector block 4 which reads the outline font data our of font input FIFO 3 and converts the coordinate data. Further, the device is equipped with a FIFO 5 which temporarily stores the converted coordinate data, a raster block 6 which reads the coordinate data in and generates a line of dots between the coordinate data, the dot memory 7 which stores the dot data, and a raster block 4 which reads the dot data in, paints out the inside of the outline of the character, and stores the resulting data in the dot memory 7 again. Therefore, the best processing speed for the system is obtained and the device scale is reducible.

4. 发明专利

JPH064055A DISPLAY DATA TRANSMITTER 失效
公开(公告)号：JPH064055A
公开(公告)日：1994-01-14
申请号：JP16147792
申请日：1992-06-19
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MANO HIROYUKI , NISHIMOTO KAZUHISA , SUZUKI TETSUYA , SHIRANE HIROAKI , KAWAI TAKAHIRO
IPC分类号： G09G3/18 , G09G5/00
摘要： PURPOSE:To secure excellent display quality and perform long-distance fast display data transmission of 10m and 80MHz without increasing the number of signal lines between a personal computer body and a liquid crystal display device by transmitting display data between the personal computer body and liquid crystal display device by using a signal of ECL signal level. CONSTITUTION:The personal computer body 1 is provided with an ECL(emitter coupled long) interface means 6 which outputs display data 10b after the PUS conversion of display data inputted from a display memory 5 and a dot clock 12 generated by a display control means 4 at least as the signal of ECL signal level; and the liquid crystal display device 2 is provided with an ECL interface input means 7 which inputs the data of ECL signal level sent from the personal computer body 1 and outputs it to a liquid crystal control means 8.

5. 发明专利

JPH05216439A MULTIGRADATION DRIVING CIRCUIT FOR LIQUID CRYSTAL 失效
公开(公告)号：JPH05216439A
公开(公告)日：1993-08-27
申请号：JP2252192
申请日：1992-02-07
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MANO HIROYUKI , SUZUKI TETSUYA , SUZUMURA SHINTARO , SHIRANE HIROAKI , FURUHASHI TSUTOMU , NISHIMOTO KAZUHISA , FUTAMI TOSHIO
IPC分类号： G02F1/133 , G09G3/36 , H04N5/66
摘要： PURPOSE:To provide the multigradation driving circuit for a liquid crystal which generates a liquid crystal impressing voltage for the multigradation display by less input of the gradation level signal. CONSTITUTION:This circuit is provided with a data latching section 1 accommodating gradation information, a current source section 2 weighted corresponding to the gradation information, a current addition section 3 adding currents from the current source section 2 according to the gradation information, a current accumulating section 5 accumulating currents added with current, a current discharging section 6 initializing the current accumulating section 5, an amplifier 7 to impress the voltage accumulated in the current accumulating section 5 to liquid crystal pixels and a monitoring section 4 adjusting the dispersion of the current accumulating section 5. By replacing the gradation information with the current quantity the multigradation display is available with less input of the gradation level signal and the effect for eliminating the increase of the number of pins of multigradation driving circuit LSI of the liquid crystal in obtained.

6. 发明专利

JPH04326323A DISPLAY CONTROLLER 失效
公开(公告)号：JPH04326323A
公开(公告)日：1992-11-16
申请号：JP9677591
申请日：1991-04-26
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MANO HIROYUKI , SHIRANE HIROAKI , SUZUKI TETSUYA , NISHIMOTO KAZUHISA , TAKAHASHI KOJI
IPC分类号： G02F1/133 , G06F3/153 , G09G3/36
摘要： PURPOSE:To decrease the reduction of a frame frequency and to execute the display of a high quality by executing the control so that data is not sent to the surplus output lines of a driver which is not connected to a display panel, in the case number of plural divided display panels and the number of output lines of the driver do not coincide with each other. CONSTITUTION:The left side screen memories LML1, LML2 of an LIFO type, and the right side screen memories LMR1, LMR2 are used for storing display data of the left side screen of liquid crystal display panels LCD divided into the left and the right, and for storing display data of the right side screen, respectively, and by scanning the left side screen and the right side screen of the liquid crystal display panel LCD toward the outside, respectively, the display is executed.

7. 发明专利

JPH07220063A REDUCTION SYSTEM FOR PICTURE DATA 失效
公开(公告)号：JPH07220063A
公开(公告)日：1995-08-18
申请号：JP1080894
申请日：1994-02-02
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： NISHIKAWA KENICHI , KUROSU YASUO , ABEI MASARU , SHIRANE HIROAKI , FUJINAWA MASAAKI
IPC分类号： H04N1/393 , G06T3/40
摘要： PURPOSE:To provide the picture data reduction system which performs a simple processing at a high speed without requiring a large-sized table and is free from loss of fine line s and paint-out of pictures. CONSTITUTION:Picture elements of output pictures b1 to bn are mapped in picture elements of input pictures a1 to am in accordance with the magnification; and with respect to determination of the picture element color of an output picture element bk as the processing object, AND between a picture element selected from peripheral input picture elements and the inverted picture element color of a picture element selected from peripheral picture elements, which are adjacent to the picture element bk and are used for determination of the picture element color of a picture element bi already subjected to reduction processing, is operated to obtain a result Ch, and the picture element to be selected for the AND operation processing is successively changed to obtain results Ch+1 and Ch+2, and the OR operation result between the picture element selected from picture elements around the output picture element bk and results Ch, Ch+1, and Ch+2 obtained by AND operation is determined as the picture element color of the output picture element bk.

8. 发明专利

JPH06167961A SYSTEM AND DEVICE FOR CHARACTER CORRECTION 失效
公开(公告)号：JPH06167961A
公开(公告)日：1994-06-14
申请号：JP32033392
申请日：1992-11-30
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： SATO HIROKO , HASEGAWA KAZUKO , WAKIZAKA SHINJI , WADA HIROSHI , SHIRANE HIROAKI , NISHIMOTO KAZUHISA , NAKAMURA KENJI , HORIUCHI YUICHI
IPC分类号： G09G5/24 , G06T5/30 , G06T11/20 , G06F15/66 , G06F15/72
摘要： PURPOSE:To obtain a character with high quality whose line width is corrected at high speed. CONSTITUTION:The coordinate data of coordinate points P0-P24 which form the contour of the character include directional attribute data representing a relative direction from a preceding coordinate point in addition to the coordinate values of the coordinate points. When the coordinate data of, for example, the coordinate point P0 is read in from a font ROM, the directional attribute data is latched, and the coordinate data of the next coordinate point P1 is also latched when it is read in from the font ROM. Those directional attribute data are decoded, and the coordinate point P0 can be corrected by corrective quantity and a corrective direction in accordance with a decoded result, and a new coordinate point P0' is set. Similarly, correction are applied to the coordinate points P1-P24, and the character whose line width of the contour consisting of new coordinate points P0'-P24' shown in broken line can be obtained.

9. 发明专利

JPH064262A DATA TRANSMISSION SYSTEM 失效
公开(公告)号：JPH064262A
公开(公告)日：1994-01-14
申请号：JP16147692
申请日：1992-06-19
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： MANO HIROYUKI , SUZUKI TETSUYA , SHIRANE HIROAKI , NISHIMOTO KAZUHISA , KAWAI TAKAHIRO
IPC分类号： G06F3/153 , G06F3/00 , G09G5/00 , H04N5/00
摘要： PURPOSE:To reduce the power consumption by using a voltage suppressing means like a voltage dividing resistance to transmit a minimum voltage required for a line receiver while matching the impedance to that of a transmission cable. CONSTITUTION:An information processor main body 7 and a display device 8 are separated from each other, and they are connected by a cable 10, and the information processor main body 7 is provided with a differential signal output means 15, and the display device 8 is provided with a differential signal input means 16, and a differential signal is transmitted from the information processor main body 7 to the display device 8. In this data transmission equipment, the differential signal output means 15 is provided with a suppressing means which suppresses the output signal in the range of the signal level where the differential signal input means 16 can logically discriminate the input signal, and the impedance is matched to the characteristic impedance of the cable by this suppressing means.

10. 发明专利

JP2001168810A AUDIO REPRODUCING DEVICE COMPATIBLE WITH DATA BROADCASTING, AND REPRODUCING METHOD 失效
公开(公告)号：JP2001168810A
公开(公告)日：2001-06-22
申请号：JP35119799
申请日：1999-12-10
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST , HITACHI ULSI SYS CO LTD
发明人： OBATA SHINICHI , FUJII YUKIO , NAKAMURA HIROSHI , SHIRANE HIROAKI , YAMAMOTO EIJI
IPC分类号： H04N5/92 , G10L19/00 , H03M7/30 , H04B14/04
摘要： PROBLEM TO BE SOLVED: To provide an audio reproducing device compatible with data broadcast and its method that can repeatedly reproduce data that are transferred in an audio decoder. SOLUTION: Relating to the audio reproducing device compatible with data broadcast provided with a system extract circuit 11 that segments a digital audio compression stream and a digital data audio file, an audio decoder 12 that decodes and reproduces the digital audio compression stream, an audio RAM 13 that is used for a frame buffer and a working memory in decode processing, and a CPU 14 that plays the roll of controlling the entire decode processing, the CPU 14 analyzes a header of the digital data audio file and stores part or all of the digital data audio file to the audio RAM 13 as data audio reproduced data as its data control, and the audio decoder 12 reads the data audio reproduced data stored in a prescribed address of the audio RAM 13 and provides an output of the data.

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