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1. 发明专利

JP2002341974A HARDWARE RESET SYSTEM BY PROGRAM 失效
公开(公告)号：JP2002341974A
公开(公告)日：2002-11-29
申请号：JP2001150268
申请日：2001-05-21
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： IKETANI KATSUNORI , ISHITANI KAZUHIRO , UEDA AKIHIRO , MIYAMOTO AKIRA , SUZUKI ATSUHIRO
IPC分类号： G06F9/38 , G06F1/24
摘要： PROBLEM TO BE SOLVED: To efficiently achieve initialization of hardware corresponding to every piece of hardware even to update of the hardware in a device and change of hardware configuration by initialization data. SOLUTION: This hardware reset system is provided with a temporary storage to hold a reset program and the initialization data, a control circuit to store the reset program and the initialization data in the temporary storage via a communication line and to initialize the hardware by controlling start and stop of the program stored in the temporary storage by a start stop control bus to transfer information about the hardware to be an object of initialization, information about the initialization data, start and termination and a setting path to connect the control circuit to read a state and management information of the hardware and to set the initialization data with the respective pieces of hardware.

2. 发明专利

JPH02166519A MICROPROGRAM CONTROL SYSTEM 失效
公开(公告)号：JPH02166519A
公开(公告)日：1990-06-27
申请号：JP32066688
申请日：1988-12-21
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： ISHITANI KAZUHIRO , WADA HIDEO
IPC分类号： G06F9/24 , G06F9/06 , G06F9/22 , G06F9/445
摘要： PURPOSE:To update a microprogram without interrupting the system operation by changing the microprogram asynchronously via a communication circuit. CONSTITUTION:A microprogram undergoes the writing and reading actions as necessary and asynchronously via a communication circuit 17 and is written into a 2nd microprogram store area of a memory. At the same time, the microprogram is loaded to a 2nd control memory via a reception circuit 3. Then the microprogram stored in a 1st control memory 5 is instantaneously shifted to a 2nd control memory 6 via a control circuit 4 which secures the synchronization between the data end report of the circuit 17 and the state of a controller and a selection circuit 11 which selects a microprogram to be used. In such a way, the microprogram is easily changed.

3. 发明专利

JPH04268925A MICROPROCESSOR 失效
公开(公告)号：JPH04268925A
公开(公告)日：1992-09-24
申请号：JP3022691
申请日：1991-02-25
申请人： HITACHI LTD , HITACHI MICRO SYSTEM KK
发明人： ISHITANI KAZUHIRO , MURE MAKOTO
IPC分类号： G06F9/22
摘要： PURPOSE:To attain various microprogram processing by a microprocessor while effectively using the storage capacity of a single control storage. CONSTITUTION:A microinstruction area 1a divided into fields 1b to 1d, an address area 1f for storing an address specifying a microinstruction to be processed next, an additional address area 1g, and a field track area 1e are stored in the control storage 1. When an address has been specified in the area 1g, a plural-address forming circuit 7a reads out also a microinstruction specified by the area 1g together with a microinstruction specified by the area 1f. A microinstruction control circuit 9 combines the read microinstructions by a pattern specified by the area 1e in each field to constitute a microinstruction and supplies the constituted microinstruction to a microinstruction processing circuit 8. Thereby, the common parts of respective microinsturctions can be used in common.

4. 发明专利

JPH0320826A MICROPROGRAM CONTROLLER 失效
公开(公告)号：JPH0320826A
公开(公告)日：1991-01-29
申请号：JP15458889
申请日：1989-06-19
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： ISHITANI KAZUHIRO , SAKURAI MASAAKI
IPC分类号： G06F9/22 , G06F9/34
摘要： PURPOSE:To shorten a processing time by performing data transfer and a control processing between a microinstruction processing circuit and a readable/ writable control storage buffer. CONSTITUTION:When a microinstruction processing circuit 8 is processed with a called microinstruction, a control storage buffer 3 shown by a microinstruction address is discriminated with a processing storage flag 21 and a processing selection flag 22 at a control circuit 22, and a processing result shown by the processing selection flag 22 is automatically stored in a processing result holding area 23 in a write permission mode by the processing storage flag 21. Meanwhile, when the processing result is read out by the microinstruction, the control storage buffer 3 is indexed based on the microinstruction address by the microinstruction, and the result is read out with the control circuit 12 which controls the readout of the processing result holding area 23, and it can be set at a processing result readout area corresponding to the processing selection flag 22.

5. 发明专利

JPS63245745A BUFFER STORAGE CONTROLLER 失效
公开(公告)号：JPS63245745A
公开(公告)日：1988-10-12
申请号：JP7744087
申请日：1987-04-01
申请人： HITACHI LTD , HITACHI COMPUTER ENG , HITACHI MICROCUMPUTER ENG
发明人： WATABE YASUO , HIBI KAZUO , HASHIMOTO YOJI , SHIMURA NOBUYUKI , ISHITANI KAZUHIRO
IPC分类号： G06F12/08
摘要： PURPOSE:To speed up data reading by transferring the data of one block data with a fixed width following the one-block data to a buffer storage device. CONSTITUTION:In case of storing data in a buffer storage, data for one block (6 bytes) and following 8 bytes are transferred from a main storage device to store the data of 72 bytes continued in the main storage in the buffer storage. When the data in the main storage device are transferred to the buffer storage, the data are stored in data parts 107-109 of the buffer storage. When data corresponding to an address applied to an address register 101 exist in the buffer storage, the leading data are read out from the buffer storage data part 108 and the leading data in the succeeding block are simultaneously read out from the data part 109.

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