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1. 发明专利

JP2003149270A METHOD FOR MANUFACTURING SEMICONDUCTOR-INSPECTING APPARATUS AND SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：JP2003149270A
公开(公告)日：2003-05-21
申请号：JP2001346899
申请日：2001-11-13
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： FUJIKI NAOTO , KAWAKAMI KENJI
IPC分类号： G01R1/073 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor-inspecting apparatus for preventing a probe from being damaged in handling by retaining a probe surface where the probe is formed. SOLUTION: When the probe 4 is to be formed, a probe protection projection 5 whose tip area is larger than that of the tip in the probe 4 is also formed. Additionally, in a positioning groove formation process for forming a positioning groove, the probe protection projection 5 is removed.

2. 发明专利

JP2000228364A METHOD OF PRODUCING EPITAXIAL WAFER AND SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000228364A
公开(公告)日：2000-08-15
申请号：JP2847699
申请日：1999-02-05
申请人： HITACHI LTD , HITACHI TOKYO ELECTRONICS
发明人： KONDO TAIICHI , KAWAKAMI KENJI , OKUDA MASAHIRO , KATAOKA MASATSUGU , AOYANAGI RYOICHI , NAKAMURA KATSUMI , KAWABE YUKIO , KOMATSU TADASHI
IPC分类号： H01L21/205 , H01L21/20
摘要： PROBLEM TO BE SOLVED: To reduce misting defect of an epitaxial wafer. SOLUTION: In an epitaxial wafer producing method, on the principal surface of a semiconductor wafer, a preheating step 1 for heating the semiconductor wafer at 950 deg.C under a hydrogen gas atmosphere and a preheating step 2 for heating the semiconductor wafer at 1,100 deg.C under a hydrogen gas atmosphere are successively performed before an epitaxial growth step 3 at 950 deg.C using SiH4 as source gas. Organic substance attached to the semiconductor wafer is resolved and removed, without producing a reaction product with the surface of the semiconductor wafer in the preheating step 1, natural oxide is removed through reduction in the preheating step 2, and then an epitaxial growth is performed on the clean surface of the semiconductor wafer, thereby preventing failures such as misting and the like in the epitaxial wafer.

3. 发明专利

JP2003077965A Inspection apparatus for semiconductor device and method of inspecting semiconductor device using same 审中-公开
标题翻译：用于半导体器件的检查装置及使用其检查半导体器件的方法
公开(公告)号：JP2003077965A
公开(公告)日：2003-03-14
申请号：JP2001266731
申请日：2001-09-04
申请人： Hitachi Ltd , Hitachi Tokyo Electronics Co Ltd , Hitachi Ulsi Systems Co Ltd , 日立東京エレクトロニクス株式会社 , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： BAN KAZUHIRO , NEZU YUICHI , KAWAKAMI KENJI , FUJIKI NAOTO , YAMAGAMI TAKASHI , NAGAKURA TSUTOMU , AMARI HIROYUKI , SUGIYAMA YUKINORI
IPC分类号： G01R31/26 , G01R1/073 , G01R31/28 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To provide a probing technique for preventing a short circuit caused when wiring contacts a semiconductor chip while securing strength of beams.
SOLUTION: A plurality of beams 11 in a double-supported-beam structure are placed in parallel on a wafer. A projection 12 is formed in the center of each beam 11 of the wafer. The projection 12 is coated with a metal film 13 as a contactor, and an electrode is formed for connection to the other side of the wafer. Wiring 14 for connecting the contactor and electrode derives the metal film 13 coated on the projection 12 from one side through the side of the beam 11 to the other side of the beam, where the wiring extends to connect the contractor and electrode, thus wiring does not extend on a surface to be inspected and the short circuit is prevented. Furthermore, the double- supported-beam structure of the beam 11 provides sufficient strength.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种用于防止当布线在确保梁的强度时接触半导体芯片时引起的短路的探测技术。解决方案：双支撑梁结构中的多个梁11平行放置在晶片上。突起12形成在晶片的每个光束11的中心。突起12涂覆有作为接触器的金属膜13，并且形成用于连接到晶片的另一侧的电极。用于连接接触器和电极的布线14将涂覆在突起12上的金属膜13从梁11的一侧延伸到梁的另一侧，其中布线延伸以连接承包件和电极，因此布线不会在要检查的表面上延伸，并且防止短路。此外，梁11的双支撑梁结构提供足够的强度。

4. 发明专利

JP2002168904A METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002168904A
公开(公告)日：2002-06-14
申请号：JP2000366496
申请日：2000-12-01
申请人： HITACHI LTD
发明人： KAWAKAMI KENJI , OKABE HITOSHI
IPC分类号： G01R31/26 , G01R1/073 , G01R31/28 , H01L21/66
摘要： PROBLEM TO BE SOLVED: To maintain a prescribed contact load to inspect an electric characteristic by sure contact, even when an arranging pitch for electrode pads is narrowed in a specimen. SOLUTION: Support beams 12 of a probe 13 formed in a substrate 11 of a contact 10 are arranged alternately in a zig-zag form, an arranging pitch P for the probes 13 is made to get smaller than the sum of a width Wb of the support beam 12 and a width Wg of a beam clearance 12a, rigidity (that is, required contact load or the like) is maintained without reducing the width Wb of the beam 12 over requirement, and the pitch P of the probe 13 is made, under the condition hereinbefore, to cope with narrowing of the arranging pitch for the electrode pads on the semiconductor chip side of the specimen, so as to inspect efficiently by a silicon contactor system in the semiconductor chip of which the size reduction and the fineness progress.

5. 发明专利

JPH10294287A TRANSFER METHOD FOR SEMICONDUCTOR WAFER OF SEMICONDUCTOR MANUFACTURE DEVICE 失效
公开(公告)号：JPH10294287A
公开(公告)日：1998-11-04
申请号：JP10458897
申请日：1997-04-22
申请人： HITACHI LTD
发明人： KAWAKAMI KENJI
IPC分类号： C30B25/12 , H01L21/20 , H01L21/205 , H01L21/26 , H01L21/324
摘要： PROBLEM TO BE SOLVED: To reduce the damage of a semiconductor wafer at the time of thermal treatment and to improve the quality of the semiconductor wafer. SOLUTION: The device is provided with a reaction container where the film forming treatment of the semiconductor wafer 1 is executed, a lamp heating the semiconductor wafer 1 at the time of film forming treatment, a susceptor 4 which is installed in the reaction container and supports the semiconductor wafer 1 at the time of film forming treatment, a transportation blade 5 guiding the carry-in/out of the semiconductor wafer 1 into/from the reaction container, lift pins 6 which repeat/support the semiconductor wafer 1 at the time of transferring the semiconductor wafer 1 to the susceptor 4 from the transportation blade 5 and a control part controlling the transfer procedure of the semiconductor wafer 1 from the lift pins 6 to the susceptor 4. At the time of transferring the susceptor 4 from the transportation blade 5 on the susceptor 4 through the lift pins 6, the warp of the semiconductor wafer 1 which is carried into the reaction container, is heated and warped is restored on the lift pins 6 and the wafer is transferred to the susceptor 4.

6. 发明专利

JPH05316018A MOBILE RADIO EQUIPMENT 失效
公开(公告)号：JPH05316018A
公开(公告)日：1993-11-26
申请号：JP11877092
申请日：1992-05-12
申请人： HITACHI LTD , HITACHI VIDEO & INF SYST
发明人： YOSHIDA JUNICHI , KAWAKAMI KENJI
IPC分类号： H04B7/26 , H04W52/02 , H04W84/02
摘要： PURPOSE:To reduce a current consumption of a reception circuit in the reception standby by implementing intermittent reception. CONSTITUTION:Control information called notice information sent from a base station in the reception standby state is received by a reception circuit 2 via an antenna 1, demodulated by a digital data demodulation circuit 4 and subject to majority processing by a majority processing circuit 5 and the result is analyzed by a microprocessor 6. On the other hand, the information is digitally converted by an A/D converter 3 and the microprocessor 6 decides number of words to be received in the control information sent repetitively based on received electric field strength whose strength is discriminated. The microprocessor 6 according to it receives only a word to be received from a head and interrupts the power for the reception circuit till a synchronizing signal at the head of succeeding control information from the head of a remaining word.

7. 发明专利

JPS6129078B2 失效
公开(公告)号：JPS6129078B2
公开(公告)日：1986-07-04
申请号：JP3555078
申请日：1978-03-29
申请人： HITACHI LTD
发明人： OONO NOBUHIKO , KAWAKAMI KENJI
IPC分类号： G11C17/00 , G11C17/06 , G11C17/14 , G11C17/18

8. 发明专利

JPS5555561A JUNCTION DESTRUCTIVE PROGRAMMABLE MEMORY CELL 失效
公开(公告)号：JPS5555561A
公开(公告)日：1980-04-23
申请号：JP12835378
申请日：1978-10-20
申请人： HITACHI LTD
发明人： OONO NOBUHIKO , KAWAKAMI KENJI
IPC分类号： G11C17/06 , G11C17/14 , H01L21/8229 , H01L27/10 , H01L27/102
摘要： PURPOSE:To enhance the current concentration of a junction destructive programmable memory cell by dividing a collector region into plural regions, providing collector electrodes in the respective regions, providing base and emitter regions at both sides of the electrode, and flowing writing current only in predetermined direction of the respective cells. CONSTITUTION:Collector regions 19, 20 are divided into plural regions, and collector electrodes 21, 22 are provided at every collector regions 19, 20. Then, base regions 5-8 and emitter regions 9-12 are provided at both sides of the collector electrodes 21, 22. Thus, writing currents from the electrode layers 13-16 flow only in predetermined direction (an arrow in the drawing) of the respective cells.

9. 发明专利

JPH0955500A FORMING METHOD OF SEMICONDUCTOR ELEMENT AND MOSFET FORMED BY THE METHOD 失效
公开(公告)号：JPH0955500A
公开(公告)日：1997-02-25
申请号：JP20589495
申请日：1995-08-11
申请人： HITACHI LTD
发明人： KAWAKAMI KENJI
IPC分类号： H01L29/78 , H01L21/336
摘要： PROBLEM TO BE SOLVED: To provide a pocket layer which restrains a short channel effect not around a high-concentration diffusion layer but around a low-concentration diffusion layer near to a gate electrode by a method wherein the pocket layer is formed using a gate electrode layer, a source electrode layer, and a drain electrode layer as a mask. SOLUTION: An N-layer (low concentration diffusion layer) 11 is formed adjacent to a gate electrode 5 where P (phosphorus) ions are implanted using a gate electrode layer 10, a source electrode layer 8, and a drain electrode layer 9 as a mask. For instance, B ions are implanted for the formation of a P pocket layer 12 around the N layer (low concentration diffusion layer) 11. By this setup, an NMOS of LDD structure equipped with the N layer 11 adjacent to the gate electrode 5 and an N layer 7 extending from the N layer 11 towards a field insulating film 3 is formed. Moreover, a pocket layer 12 which restrains a short channel effect is formed only around the N layer 11.

10. 发明专利

JPS55146697A WRITING CIRCUIT FOR JUNCTION DESTRUCTIVE PPROM 失效
公开(公告)号：JPS55146697A
公开(公告)日：1980-11-15
申请号：JP5348979
申请日：1979-05-02
申请人： HITACHI LTD
发明人： KAWAKAMI KENJI , OONO NOBUHIKO
IPC分类号： G11C17/00 , G11C17/18
摘要： PURPOSE:To make programming in a package state possible by suppressing the operation of a PNPN element with an extremely small current by grounding the base of the NPN transistor of the PNPN element via the element. CONSTITUTION:The base of NPN transistor TrQ2 constituting the PNPN element is grounded via resistance R3. As a result, an extremely small current such as a leakage current, when appearing at the collector of PNPTrQ1, flows to the ground via resistance R3 without flowing to the base of NPNTrQ2 to turn the PNPN element ON. Therefore, not less than two P-ROM ICs whose outputs are connected mutually can be programmed in the package state.

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