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1. 发明专利

JP2002108567A STORAGE CONTROL APPARATUS 失效
公开(公告)号：JP2002108567A
公开(公告)日：2002-04-12
申请号：JP2000300563
申请日：2000-09-28
申请人： HITACHI LTD , HITACHI SOFTWARE ENG
发明人： IDO KENJI , GOTO YOICHI , YOKOHATA SHIZUO , HONMA SHIGEO , YOSHINO TOSHIYUKI
IPC分类号： G06F12/08 , G06F3/06 , G06F13/12 , G06F15/177
摘要： PROBLEM TO BE SOLVED: To process an I/O to be preferentially processed without being affected by any other I/O processing while maintaining performance by dividing the I/O processing into the priority processing and the non-priority processing, and processing the non-priority I/O while suppressing the processing. SOLUTION: A storage control apparatus 301 is provided with a memory 505 common to I/O processing control parts 501-504, and manages information for dividing plural I/O processing into the priority processing and the non- priority processing, and for controlling them in the memory 505. Thus, it is possible to operate the non-priority I/O while suppressing its processing.

2. 发明专利

JP2014206982A ストレージシステムおよびそのデータ制御方法有权
标题翻译：存储系统及其数据控制方法
公开(公告)号：JP2014206982A
公开(公告)日：2014-10-30
申请号：JP2014095926
申请日：2014-05-07
申请人：株式会社日立製作所 , Hitachi Ltd
发明人： NOBORIKAWA YOSHIYUKI , HONMA SHIGEO
IPC分类号： G06F3/06 , G06F3/08 , G06F12/00 , G06F12/16
摘要：【課題】管理が不要な記憶領域を管理しないフラッシュパッケージのパッケージコントローラを提供する。【解決手段】バックアップ対象とされる第一の論理記憶領域に対して更新データの書き込み要求を受信すると、更新前のデータを維持した状態で、第一の物理記憶領域をバックアップ用記憶領域として管理し、第一の論理記憶領域に新たに第二の物理記憶領域を割り当てて更新データを書き込む。バックアップ非対象とされる第二の論理記憶領域に対して更新データの書き込み要求を受信すると、第二の論理記憶領域に割り当てられていた第三の物理記憶領域を無効記憶領域として管理し、第二の論理記憶領域に新たに割り当てられた第四の物理記憶領域に更新データを書き込む。前記第一の物理記憶領域を用いて、第一のLUのバックアップデータを提供し、第三の物理記憶領域に格納された更新前のデータを消去する。【選択図】図1
摘要翻译：要解决的问题：提供不管理不需要的存储区域的闪存包的包控制器。解决方案：当接收到作为备份对象的第一逻辑存储区域中的更新数据的写入请求时，物理存储区域被作为用于备份的存储区域进行管理，其中在更新数据被维护的状态下，并且第二物理存储区域被新分配给第一逻辑存储区域，并且更新数据被写入。当接收到作为备份非对象的第二逻辑存储区域中的更新数据的写入请求时，将分配给第二逻辑存储区域的第三物理存储区域作为无效存储区域进行管理，更新数据被写入新分配给第二逻辑存储区域的第四物理存储区域。通过使用第一物理存储区域提供第一LU（逻辑单元）的备份数据，并且删除存储在第三物理存储区域中的预更新数据。

3. 发明专利

JP2002196980A DATA LOADING METHOD AND DEVICE 审中-公开
公开(公告)号：JP2002196980A
公开(公告)日：2002-07-12
申请号：JP2001325763
申请日：2001-10-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YAMAMOTO AKIRA , TSUBOI TOSHIAKI , HONMA SHIGEO , NAKAMURA KATSUNORI , KANBAYASHI KIMISAKI , KITAJIMA HIROYUKI , KURANO AKIRA , NOZAWA MASASHI
IPC分类号： G06F12/08 , G06F3/06
摘要： PROBLEM TO BE SOLVED: To solve the problem that, when an access pattern from a central processing unit to a disk device is changed with time in a same storage region, the using efficiency of a cache memory cannot be held optimally, because the operation mode in the divided and individual storage region of the disk device is fixed. SOLUTION: A disk control device is connected to the disk device and the central processing unit and provided with the cache memory with a physical region on the disk device set to a cache control unit. When no data in a cache control unit including a region to be an access target exists in the cache memory inside, only data in the region to be the access target of the central processing unit is loaded in the cache memory. In this case, when there is an access to data except for those already stored in the cache memory among the data in the cache control unit, the data except for those already stored in the cache memory is loaded in the cache memory.

4. 发明专利

JP2000227868A BACKUP ACQUIRING METHOD AND COMPUTER SYSTEM 失效
公开(公告)号：JP2000227868A
公开(公告)日：2000-08-15
申请号：JP34425999
申请日：1999-12-03
申请人： HITACHI LTD
发明人： YAMAKAMI KENJI , ARAKAWA TAKASHI , HONMA SHIGEO , KITAMURA MANABU
IPC分类号： G06F3/06 , G06F12/00
摘要： PROBLEM TO BE SOLVED: To backup data, which are to be used by a computer to use the CKD format of a main frame or the like, with a miniaturized computer to use the fixed length block format of a personal computer or work station. SOLUTION: A storage device 300 provided with mutually different first and second interfaces 320 and 330 is connected to a host 100 having a first interface 110 and a host 200 having a second interface 210. The host 100 stores data through the first interface 110 into the storage device 300. The host 200 transforms the storage format of the data on the first interface to the storage format of the data on the second interface, acquires the storage position information of the data to be backed up, reads the data out of the storage device 300 on the basis of that storage position information and preserves them in a backup device 290.

5. 发明专利

JP2543519B2 失效
公开(公告)号：JP2543519B2
公开(公告)日：1996-10-16
申请号：JP8713887
申请日：1987-04-10
申请人： HITACHI LTD
发明人： HONMA SHIGEO , MYAZAKI MICHIO
IPC分类号： G06F11/10 , G11B20/18

6. 发明专利

JPH03246713A METHOD AND DEVICE FOR CONTROLLING STORAGE DEVICE 失效
公开(公告)号：JPH03246713A
公开(公告)日：1991-11-05
申请号：JP4245290
申请日：1990-02-26
申请人： HITACHI LTD
发明人： YAMAMOTO AKIRA , SATO TAKAO , HONMA SHIGEO , AZUMI YOSHIHIRO , KUWABARA YOSHINAGA , KITAJIMA HIROYUKI
IPC分类号： G06F12/08 , G06F3/06
摘要： PURPOSE:To disperse the load of input and output processings to be executed between disk devices in a disk device group, and to improve the parallel degree of the input and output processings by selecting the disk device being in an arbitrary free state in the disk device group. CONSTITUTION:When a read request which needs to execute an access to a disk device is received from a CPU with respect to a certain disk device group, a controller 203 selects one set of arbitrary disk device being in a free state in disk device groups A-C. In the case the disk device being in a free state does not exist at all, the controller allows its read request to wait. On the other hand, in the case a write request which needs to execute an access to the disk device is received, one set of specific disk device in the disk device group is selected with respect to its write request. In such a way, input and output processings can be dispersed between the disk devices within a range in which reliability is not spoiled, and the parallel degree of the input and output processings which can be executed by the controller.

7. 发明专利

JPH03184144A METHOD AND DEVICE FOR CONTROL OF CACHE 失效
公开(公告)号：JPH03184144A
公开(公告)日：1991-08-12
申请号：JP32339689
申请日：1989-12-13
申请人： HITACHI LTD
发明人： YAMAMOTO AKIRA , HONMA SHIGEO , AZUMI YOSHIHIRO , KUWABARA YOSHINAGA , KURANO AKIRA , NOZAWA MASASHI , KITAJIMA HIROYUKI
IPC分类号： G06F3/06 , G06F12/08
摘要： PURPOSE:To largely increase a range where the write processing can be performed at a high speed by completing the write processing at a stage when data are stored even though a subject record is not stored in a cache memory yet at a writing time point. CONSTITUTION:A controller 23 receives a write request from a data processor 200 for a record to be written and furthermore receives the data to be written into the subject record from the processor 200 when the record is not stored in a cache memory 26 yet. Then the controller 23 stores the received data in the memory 26 and reports the end of the write processing to the processor 200 to check whether the write subject record which writes the data stored in the memory 26 is stored in a storage 27 or not. If so, the data stored in the memory 26 are written into the write subject record in the storage 27. If not, the write of the data stored in the memory 26 is discontinued and this fact is reported to the processor 200.

8. 发明专利

JPH02264335A METHOD AND DEVICE FOR FAULT PROCESSING 失效
公开(公告)号：JPH02264335A
公开(公告)日：1990-10-29
申请号：JP8524589
申请日：1989-04-04
申请人： HITACHI LTD
发明人： MURATA TOMOHIRO , AKATSU MASAHARU , KURIHARA KENZO , HONMA SHIGEO
IPC分类号： G06F11/00 , G06F12/08 , G06F12/16
摘要： PURPOSE:To surely write holding data in a disk by executing collective write operation from a cache to the disk asynchronously with the write operation of a host computer to the disk. CONSTITUTION:When a processor 103 in a disk controller 1020 is accessed from the host computer 100, it decides for what disk drive this access is. The processor 103 issues a lock request for the disk drive 1100, for instance. When the reply of the success of lock acquisition is inputted, it requests a command from a channel controller 101. When it receives the command from the channel controller 101, it recognizes the track number and the record number of an object to be accessed. The processor 103 retrieves a track table 3801 for the disk driver 1000, and decides whether a slot for it is arranged on the cache or not.

9. 发明专利

JPH0235544A CACHE MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPH0235544A
公开(公告)日：1990-02-06
申请号：JP18471788
申请日：1988-07-26
申请人： HITACHI LTD
发明人： HONMA SHIGEO , KUWABARA YOSHINAGA , SERIZAWA YOSHIKO , NAGASAWA MITSUO , AZUMI YOSHIHIRO
IPC分类号： G06F12/08 , G06F12/12
摘要： PURPOSE:To improve a hit rate by decrease the order of subsequent expelling from a cache memory when a request to access data excellent from the cache memory in the past is generated again. CONSTITUTION:An MPU 20 controls the whole disk cache controller 11 according to a microprogram on a RAM 21. The cache memory 60 is stored with data of high access frequency from a CPU in track units and a directory memory 25 is stored with information for controlling the data stored on the cache memory 60. This directory memory 25 decreases the order of subsequent expelling of data from the cache memory 60 if the request to access the data expelled from the cache memory 60 in the past is generated again.

10. 发明专利

JPS6292022A CONTROL SYSTEM FOR TRANSFER OF DATA 失效
公开(公告)号：JPS6292022A
公开(公告)日：1987-04-27
申请号：JP23113885
申请日：1985-10-18
申请人： HITACHI LTD
发明人： HONMA SHIGEO
IPC分类号： G06F13/38 , G06F3/06 , G06F12/08 , G06F13/10 , G11B20/10
摘要： PURPOSE:To shorten the connecting time by starting a pre-reading action to a buffer before reception of the next reading command and after the end of a transfer waiting state. CONSTITUTION:A command chain is carried out by a channel 2, for example, through an electronic computer system having a double transfer speed as much as a DKU. In such a case, a pre-reading action is started to a data buffer 44 after a desired sector is fixed. However no interruption signal is applied to the channel 2. This interruption signal is applied when a prescribed time passed after a pre-reading buffering action is started. Thus the interruption signal is applied when the disk controllers DKC3 and 4 buff completely the data of the L/2-byte length. As a result, the transfer actions are through at a time between the sides of the disk controllers DKU6 and 6 and the side of the channel 2. Thus, the connecting time between the channel 2 and the DKC3 and 4 is minimized.

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