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1. 发明专利

JPS55100735A OSCILLATION CIRCUIT 失效
公开(公告)号：JPS55100735A
公开(公告)日：1980-07-31
申请号：JP707979
申请日：1979-01-26
申请人： HITACHI LTD , HITACHI OME ELECTRONIC CO
发明人： KAWAMOTO MIKIHIKO , IENAKA MASANORI
IPC分类号： H03K3/013 , H03K3/0231
摘要： PURPOSE:To prevent a disturbance signal from mixing by forming in IC a method of stopping oscillation operation, by providing a switching transistor which supplies forcibly an OFF voltage to the base of a differential transistor on the output side. CONSTITUTION:When control signal Vc is low in level and transistor TrQ6 is OFF, an oscillation circuit composed of a couple of differential transistors TrQ1 and TrQ2, a current Miller circuit (TrQ3 and TrQ4), TrQ5, and capacitor C oscillates because the inverted voltage of the differential transistor circuit has hysteresis characteristics (Vvand VL). With control circuit Vc at a high level, TrQ6 is ON and differential transistor Q2 is forced to conduct, so that oscillation operation will stop.

2. 发明专利

JP2001102874A SURGE PROTECTING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JP2001102874A
公开(公告)日：2001-04-13
申请号：JP27966599
申请日：1999-09-30
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YUKITA MASAHIRO , TAKESHITA RITSUJI , IENAKA MASANORI
IPC分类号： H03F1/52
摘要： PROBLEM TO BE SOLVED: To provide a surge protecting circuit capable of protecting an amplifier from a surge voltage even when the breakdown strength of each of transistors is lowered. SOLUTION: This semiconductor integrated circuit provided with a push-pull output circuit 21 equipped with two output transistors M1 and M2 connected in series between a first power voltage terminal VCC and a second power voltage terminal GND is constituted by providing a surge detecting circuit 51 for detecting an excessive voltage impressed to the power supply voltage terminal VCC, a cutoff means 23 for turning the output transistors M1 and M1 into high resistance state with the surge detecting means and an excessive voltage distributing means 22 for dividing the excessive voltage when this excessive voltage is impressed to the power supply voltage terminal VCC and distributing the excessive voltage to the said plural output transistors M1 and M2.

3. 发明专利

JPH1032437A POWER AMPLIFIER 失效
公开(公告)号：JPH1032437A
公开(公告)日：1998-02-03
申请号：JP18910396
申请日：1996-07-18
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YUKITA MASAHIRO , IENAKA MASANORI , TAKESHITA RITSUJI , HOSODA SHOICHI
IPC分类号： H03F3/45 , H03F3/30 , H03F3/68
摘要： PROBLEM TO BE SOLVED: To compatibly attain high output power and high stability even under a low power source voltage by integrating a feedback capacitor forming a local negative feedback circuit with an inverted Darlington connection circuit and a phase advance capacitor suppressing oscillation on a semiconductor substrate. SOLUTION: A pushing circuit CKT consists of the inverted Darligton connection circuit consisting of the combination of a PNP-type transistor TRQ 3 and NPN-type TRQ 1 so that the maximum value of a final amplification output signal from an output terminal P4 can be amplified to a level which is very close to a power source voltage VCC. On the other hand a pulling circuit CKT also consists of the inverted Darlington connection circuit consisting of the combination of a PNP-type transistor TRQ 4 and NPN-type TRQ 2 so that a final output value of a terminal P4 can be amplified to a level which is very close to a ground potential. Thereby, a feedback capacitor forming the local negative feedback circuit and the phase advance capacitor suppressing oscillation can be integrate-formed on the semiconductor substrate.

4. 发明专利

JPH07212142A AUDIO POWER AMPLIFIER 失效
公开(公告)号：JPH07212142A
公开(公告)日：1995-08-11
申请号：JP434394
申请日：1994-01-20
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YUKITA MASAHIRO , IENAKA MASANORI
IPC分类号： H03F1/02 , H03F3/183 , H03F3/30 , H03F3/34
摘要： PURPOSE:To stably obtain high output by a comparatively low power supply voltage without depending on a snubber circuit by forming a gain limiting circuit which suppresses a voltage gain fed back by a level shift loop which sets input and output voltages at the same potential. CONSTITUTION:Transistors TrQ2, Q3, Q4, and Q5 and a constant current circuit 11 form the level shift loop which sets an output terminal Vout and an input terminal Vin at the same potential. The level shift loop uses a level shift effect by a voltage between the base and emitter of each transistor, and no voltage gain is generated. First and second resistors R1, R2 form the gain limiting circuit. The circuit suppresses the feedback of the voltage gain generated by making the emitter resistance of an npn TrQ1 function as the collector load resistance of a pnp TrQ2 at an inverted Darlington circuit 3. Consequently, the high output can be stably obtained by a low power supply voltage without depending on the snubber circuit.

5. 发明专利

JPH0376318A DIGITAL/ANALOG CONVERTER OR DELTA SIGMA MODULATION CIRCUIT IN ANALOG/DIGITAL CONVERTER 失效
公开(公告)号：JPH0376318A
公开(公告)日：1991-04-02
申请号：JP21136689
申请日：1989-08-18
申请人： HITACHI LTD
发明人： ISO YOSHIMI , YOSHIDA MITSUE , ABETA AKIRA , ARAI TAKAO , IENAKA MASANORI , MAIO KENJI , WATANABE KAZUO
IPC分类号： H03M3/04 , H03M3/02
摘要： PURPOSE:To make the operation stable and to expand the dynamic range by approaching the degree of an integration circuit to a characteristic of the quadratic order when signal level is high, and approaching the degree of the integration circuit to a characteristic of the 3rd order when signal level is low. CONSTITUTION:The relation of input and output signals of a delta-sigma modulation circuit 3 is expressed in equation I, where X, Y are input and output signals, Q is quantization noise, A is a multiplication gain of a variable multiplier 11 and Z is a sample delay of a delay device 14. With A=0 set, the degree of an integration circuit reaches a characteristic of quadratic degree as Y=X+Q(1-Z ) and with A=1 set, the degree of the integration circuit reaches a characteristic of 3rd degree as Y=X+Q(1-Z ) . For example, assuming as A=1/256 until input levels of 0--4dB, as A=1/16 until input levels of -4dB--8dB, and as A=1/8 until input level of

6. 发明专利

JPH0225570B2 失效
公开(公告)号：JPH0225570B2
公开(公告)日：1990-06-04
申请号：JP7654781
申请日：1981-05-22
申请人： HITACHI LTD
发明人： IENAKA MASANORI
IPC分类号： H04B1/16 , H03J1/02 , H03J3/14

7. 发明专利

JPS63211829A FM RECEIVER 失效
公开(公告)号：JPS63211829A
公开(公告)日：1988-09-02
申请号：JP2866588
申请日：1988-02-12
申请人： HITACHI LTD
发明人： IENAKA MASANORI
IPC分类号： H04H1/00 , H04H40/45 , H04H40/72
摘要： PURPOSE:To contrive the improvement of the S/N by applying a detection signal to a 1st and a 2nd variable impedance means so as to decrease the imped ance gradually by the reduction in the level of an FM intermediate frequency signal. CONSTITUTION:When the level of an FM intermediate frequency input signal VIFIN is reduced remarkably, a collector current of a transistor (TR) Q24 is increased and the emitter input resistance of TRs Q20-Q23 is decreased. Thus, the 1st and 2nd variable impedance circuits 61, 62 are adopted so as to drive out a high frequency noise component in an output signal at terminals Nos. 14, 15 to a ground through capacitors C24, C25 and the 1st and 2nd variable impedance circuits 61, 62 having a low impedance in the even of the remarkable decrease in the level of the FM intermediate frequency input signal VIFIN, then the S/N is improved further.

8. 发明专利

JPS634370B2 失效
公开(公告)号：JPS634370B2
公开(公告)日：1988-01-28
申请号：JP13291180
申请日：1980-09-26
申请人： HITACHI LTD
发明人： ISO YOSHIMI , IENAKA MASANORI
IPC分类号： H03G3/34 , H04B1/10 , H04H1/00 , H04H40/72

9. 发明专利

JPS6262106B2 失效
公开(公告)号：JPS6262106B2
公开(公告)日：1987-12-24
申请号：JP711879
申请日：1979-01-26
申请人： HITACHI LTD
发明人： KASHIMA HIDEO , IENAKA MASANORI , KOMINAMI YASUO
IPC分类号： H04N5/60 , H04H1/00 , H04H40/36

10. 发明专利

JPS62274917A PHASE SYNCHRONIZATION DETECTING CIRCUIT 失效
公开(公告)号：JPS62274917A
公开(公告)日：1987-11-28
申请号：JP11738386
申请日：1986-05-23
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： NAKAGAWA JUNICHI , KIMURA HIDEFUMI , KUWAMOTO YOSHITOMO , IENAKA MASANORI , WATANABE HIDEAKI
IPC分类号： H03K5/26 , G01R25/00 , H03L7/089 , H03L7/095
摘要： PURPOSE:To obtain a phase difference as a phase synchronizing signal for conversion to level by providing the first circuit, which generates the characteristic of an output pulse width to an input signal phase difference where there is a blind sector where the output pulse width is zero, and a sampling circuit which samples the comparison output of the first circuit and using the output of the sampling circuit as the phase synchronizing signal. CONSTITUTION:Assuming that the delay time of each logic circuit is equally tau, leading parts of negative pulses of signals UP and DW are cut away in a pulse width discriminating circuit 8 by a delay time T1=3tau of delay elements 10 and 11. That is, a negative pulse width TP of a signal L or M is given by TP=¦Ttheta¦+tau-T1 if the fall phase difference between signals R and V is defined as T0. In case of T1>=tau, the signal L or M is certainly in the low level as it is. In case of TP

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