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1. 发明专利

JP2002280402A SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JP2002280402A
公开(公告)日：2002-09-27
申请号：JP2001083180
申请日：2001-03-22
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： ARAI HIROSHI , NAGASHIMA NOBUAKI , KASAI NORIHIKO , SEKI ISAO
IPC分类号： H01L21/56 , H01L23/31
摘要： PROBLEM TO BE SOLVED: To suppress the occurrence of voids. SOLUTION: A semiconductor device has a semiconductor chip having a square main surface, a wiring board having the chip on its main surface, and a resin sealant which seals the chip and has a square main surface faced to the main surface of the chip. The semiconductor device also has a gate cutting trace section formed on the side face of the resin sealant along the first edge of the main surface of the sealant. The first edge of the main surface of the sealant is extended along the first edge of the main surface of the semiconductor chip, and the second edge of the main surface of the sealant crossing the first edge of the main surface of the sealant is extended along the second edge of the main surface of the chip crossing the first edge of the main surface of the chip. On the cross section of the chip perpendicular to the second edge of its main surface, the cross-sectional area of the region between the main surfaces of the wiring board and resin sealant on the outside of the side face of the semiconductor chip is smaller than that of the region between the main surfaces of the chip and sealant.

2. 发明专利

JP2002110721A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002110721A
公开(公告)日：2002-04-12
申请号：JP2000301952
申请日：2000-10-02
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： GOTO MASAKATSU , KASAI NORIHIKO
IPC分类号： H01L25/18 , B29C45/14 , H01L21/56 , H01L25/065 , H01L25/07
摘要： PROBLEM TO BE SOLVED: To improve yield of semiconductor device. SOLUTION: In a method for manufacturing a semiconductor device, on the principal surface of a substrate a plurality of semiconductor chips which are mounted at prescribed intervals from a first edge of the principal surface toward a second edge opposing the first edge are disposed inside a cavity, or a forming mold with the substrate. Then, a step is provided, where a resin is injected inside the cavity from the first edge toward the second edge of the principal surface on the substrate to form a resin encapsulant for encapsulating the plurality of the semiconductor chips in batch, and additionally a step is provided where a cleaning process is conducted on the principal surface of the substrate, before the step of forming the resin encapsulant.

3. 发明专利

JP2000114288A METHOD AND DEVICE FOR POTTING, AND MANUFACTURE OF SEMICONDUCTOR DEVICE USING THEM 失效
公开(公告)号：JP2000114288A
公开(公告)日：2000-04-21
申请号：JP28363398
申请日：1998-10-06
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： KASAI NORIHIKO
IPC分类号： B65D35/28 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To allow faster application of a liquid resin and higher accuracy in applied amount. SOLUTION: A flexible tube-type syringe 10 provided with a discharge port through which a sealing resin 2 is charged or it is discharged, a pressurizing roller 11 which pressurizes and deforms the syringe 10 from its outside so that the sealing resin 2 filled in the syringe 10 is forced to go out through the discharge port, a syringe holder 12 which engages with a syringe supported part 10b of the end part on the side opposite to the discharge side of the syringe 10 for supporting the syringe 10, and a needle 13 fitted to a needle-attaching part 10a of the end part on the discharge side of the syringe 10 are provided. As a result, the syringe 10 is pressurized and deformed by the pressurizing roller 11, and the sealing resin 2 is discharged through the discharge port for applying the sealing resin 2.

4. 发明专利

JPH10135258A MULTIPLE CONNECTED WIRING BOARD AND MANUFACTURE OF SEMICONDUCTOR DEVICE USING THE SAME 失效
公开(公告)号：JPH10135258A
公开(公告)日：1998-05-22
申请号：JP28780096
申请日：1996-10-30
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： KASAI NORIHIKO
IPC分类号： H01L23/12 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To prevent molding failure in the molding process of a multiple connected wiring board, by a method wherein the dimension in the width direction of the multiple connected wiring board is formed to be equal to the dimension in one direction of a semiconductor device which is formed by cutting the multiple connected wiring board into chip regions. SOLUTION: A multiple connected wiring board 1 is composed of, e.g. epoxy resin, and so formed that the necessary number of, e.g. five, chip regions 1a which are cut out for wiring boards 3 of semiconductor devices 2 of a ball grid array(BGA) are continuously formed. The length of the multiple connected wiring board 1 is L1 and the width is L2 . The length L1 is constituted of the total dimension of the five chip regions 1a and four waste regions 1b sandwiched by the chip regions 1a. The width L2 constituted of the dimension of a single chip region 1a is equal to the dimension in one direction of the wiring board 3 of the semiconductor device 2. Thereby only cutting in the width direction is performed, in the work for making the respective chips of the multiple connected wiring board 1 wherein the width L2 serves as it is in the semiconductor devices 2.

5. 发明专利

JPH08148643A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, MANUFACTURE THEREOF, AND RESIN MOLDING DIE THEREFOR 失效
公开(公告)号：JPH08148643A
公开(公告)日：1996-06-07
申请号：JP28572794
申请日：1994-11-18
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI HOKKAI SEMICONDUCTOR
发明人： NISHIZAWA HIROTAKA , MIURA TOMOYOSHI , ANJO ICHIRO , YAMADA TOSHIO , SEKINE YASUSHI , OBARA TETSUJI , HANABUSA YOSHIAKI , SUGANO TOSHIO , YAMAGUCHI YASUNORI , SAWADA JIRO , YAMAMURA MASAHIRO , ISHIHARA MASAMICHI , MORITA SADAO , ARAKI TAKASHI , TAKEURA SHINOBU , FUDA MUTSUO , KASAI NORIHIKO , GOTO MASAKATSU
IPC分类号： H01L25/18 , H01L21/56 , H01L25/065 , H01L25/07
摘要： PURPOSE: To provide a miniature, high-performance multichip module and a manufacturing technique therefor. CONSTITUTION: Lead frames mounted with a semiconductor chip are stacked up to a specified number of layers, and sealed in a lump with resin to form a package 2. The obtained package 2 is placed on a mother socket 3. The outer leads 6 of the lead frames, led out of the side of the package 2, are electrically connected with the leads 7 of the mother socket that extend in the direction orthogonal to the direction of the extension of the outer leads 6, and a DRAM module 1 is thereby formed.

6. 发明专利

JP2002319595A METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002319595A
公开(公告)日：2002-10-31
申请号：JP2001123711
申请日：2001-04-23
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： GOTO MASAKATSU , KASAI NORIHIKO
IPC分类号： B29C45/26 , B29C45/14 , B29K105/20 , B29L31/00 , H01L21/56 , H01L23/29 , H01L23/31
摘要： PROBLEM TO BE SOLVED: To suppress generation of voids. SOLUTION: The method for manufacturing a semiconductor device comprises a step for preparing a wiring board having a plurality of device regions, each arranged with a semiconductor chip, on one major surface, polygonal cavities arranged on one major surface of the wiring board to cover each device region and a plurality of gates arranged along one side of the cavities, and a step for injecting resin into the cavities through the plurality of gates to resin sealing the plurality of semiconductor chips. In the resin sealing step, each semiconductor chip is arranged such that the side thereof is inclining against the macroscopic flow direction of resin in the cavity.

7. 发明专利

JPH09239787A MOLD AND PRODUCTION OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH09239787A
公开(公告)日：1997-09-16
申请号：JP4973096
申请日：1996-03-07
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： KASAI NORIHIKO
IPC分类号： B29C45/26 , B29C45/02 , B29C45/14 , B29K105/20 , B29L31/34 , H01L21/56
摘要： PROBLEM TO BE SOLVED: To enhance productivity in a mold process of a laminated package. SOLUTION: A mold is constituted so that a product positioning pin 14 is allowed to pierce through an intermediate mold 11, for example, made of paper and a lead frame 9 between a lower mold 3 and an upper mold 2 to laminate and position the intermediate mold and the lead frame and the intermediate mold 11 and the lead frame 9 are clamped between both molds 2, 3 and uniformly and closely brought to a contact state by the compression deformation of the intermediate mold 11 to prevent the generation of burr and the laminated package forming part 15 surrounding a semiconductor pellet 8 is formed on the lead frame 9 to be felled with a resin to form a laminated package. The intermediate mold 11 made of paper has a dividing structure such as a perforation capable of separating the intermediate mold 11 from the laminated package after the completion of molding and is impregnated with a release agent if necessary to be made disposable so as to dispense with cleaning.

8. 发明专利

JPS63257254A GLASS-SEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63257254A
公开(公告)日：1988-10-25
申请号：JP9087287
申请日：1987-04-15
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： KASAI NORIHIKO
IPC分类号： H01L23/02 , H01L23/50
摘要： PURPOSE:To enhance the bonding strength between a lead and low-melting glass by a method wherein a through hole is made at one part of the lead coming into contact with the low-melting glass so that an area where the lead comes into contact with the low-melting glass can be expanded. CONSTITUTION:The surface of an insulating substrate 1 excluding a recessed part 3 is coated with low-melting glass 4. Leads 5 are fixed temporarily on the glass 4 by a bonding method. Through holes 6 are made at one part of the leads 5 coming into contact with the glass. Then, when the leads 5 are pressed to the glass 4, the through holes 6 made at the leads 5 are engaged with the glass 4; accordingly, the leads 5 are fixed to the substrate 1 surely. By this setup, the bonding strength between the leads 5 and the glass 4 can be enhanced.

9. 发明专利

JPS6223121A WIRE-BONDING DEVICE 失效
公开(公告)号：JPS6223121A
公开(公告)日：1987-01-31
申请号：JP16194985
申请日：1985-07-24
申请人： HITACHI HOKKAI SEMICONDUCTOR , HITACHI LTD
发明人： SEKI ISAO , KASAI NORIHIKO
IPC分类号： H01L21/60 , H01L21/68 , H01L21/683
摘要： PURPOSE:To prevent the state that the body to be bonded levitates from the sample stand and to enable a stable wire-bonding by a method wherein an elastic member with a shape by which the warpage of the back surface of the body to be bonded can be absorbed is laid on the sample stand. CONSTITUTION:An elastic member 9, such as rubber, is formed in a ring shape in such a way as to abut on the edge parts of the bottom surface of a base 7, and, a groove part 10 is provided in the outside peripheral part thereof to form a nearly U shape cross section. First, the base 7 is conveyed on a sample stand 6 with the elastic member 9 bonded on the surface, and is placed thereon. At this time, if the back surface of the base 7 is warped, gaps generate in the edge parts of the base 7. When a such the base is subjected to vacuum drawing through a vacuum attracting hole 11, the base 7 is pulled to the direction shown by an arrow A. By this action, the point parts 12 of the ringed outside part of the elastic member 9 warp upwardly to the direction shown by an arrow B and the recessed parts of the base 7 are fixed.

10. 发明专利

JPS6298757A GLASS-SEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6298757A
公开(公告)日：1987-05-08
申请号：JP23743085
申请日：1985-10-25
申请人： HITACHI HOKKAI SEMICONDUCTOR , HITACHI LTD
发明人： KASAI NORIHIKO
IPC分类号： H01L23/50 , H01L23/10
摘要： PURPOSE:To enable the sure fixation of a lead even when there is nonuniformity in the thickness of the end portion of an inner lead or in the thickness of sealing glass, by providing a projection on the lower side of the end portion of the inner lead. CONSTITUTION:A lead 16 is superposed on a base 11 and then it is knocked in the base 11 by a stamper 1. Thereby a projection 17 formed in the end portion 16a of each inner lead is driven into sealing glass 14, and each and every lead is thereby fitted surely and closely to the sealing glass 14 even when there is some nonuniformity in the thickness of the lead 16 or the thickness of the sealing glass 14. In other words, the nonuniformity in the thickness of the lead 16 or the thickness of the sealing glass 14 is absorbed by the height H of the projection 14. In a wire bonding process subsequent to the above, therefore, ultrasonic vibrations can be given while a sufficient bonding load is applied to each and every inner lead, and thus firm wire bonding can be effected.

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