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1. 发明专利

JPS6059970A STEPUP CIRCUIT 失效
公开(公告)号：JPS6059970A
公开(公告)日：1985-04-06
申请号：JP16457583
申请日：1983-09-07
申请人： HITACHI LTD , HITACHI HARAMACHI DENSHI KOGYO
发明人： MIYAGAWA NOBUAKI , YAZAWA YOSHIAKI , MUKAI TOUJI , IKEDA TAKAHIDE , KAMEI TATSUYA , URUNO TOSHIO , OOZEKI SHIYOUICHI
IPC分类号： H02M7/25 , H02M3/07 , H02M7/21
摘要： PURPOSE:To improve the stepup performance of a stepup circuit by obtaining a double voltage in a charge pump system, charging a capacity via a blocking diode by the voltage, and then stepping up the voltage by the pulse operation to alter the voltage of a substrate. CONSTITUTION:An initial charge controllers 100, 150, 200, 250 are formed of transistors 9, 3, 4, and an inverter made of static capacity 11, a charging circuit 300 which includes transistors 7, 14 and a static capacity 13 is formed, and a stepup controller 400 is further formed of a transistor 6, thereby obtaining the double voltage of the power source voltage at a point B. The voltage is stepped up by a switch circuit 450 which includes transistors 15, 17, a charging circuit 500 having static capacity 21, and a stepup controller 600 which includes transistors 19, 20 to produce an output. Accordingly, the influence of the substrate effect of the MOS transistor 14 can be eliminated, and a voltage higher than the power source voltage can be generated by one chip.

2. 发明专利

JPS58122765A SEMICONDUCTOR RESISTANCE 失效
公开(公告)号：JPS58122765A
公开(公告)日：1983-07-21
申请号：JP347082
申请日：1982-01-14
申请人： HITACHI LTD , HITACHI HARAMACHI DENSHI KOGYO
发明人： URUNO TOSHIO , MIYAGAWA NOBUAKI , IKEDA TAKAHIDE
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/06
摘要： PURPOSE:To form a high accuracy poly Si resistance by a method wherein, in one LSI, the value of poly Si resistance having a gate is detected and compared with the previously set value, and thus the voltage impressed on the gate is controlled. CONSTITUTION:The binary signal of the resistance value correction command is inputted into terminals 17, thus switch elements 7-10 selectively open and close, and accordingly is CR-oscillated 14 by odd-numbered stage inverters 13, a resistance element 3, and a capacitor 11. After the output wave form is arranged by an inverter 15, the logical sum 19 is obtained with clock signal 22, and accordingly the output is counted 21. On the other hand, a desired value is set 26 and compared 24 with the counted value 21 resulting in the emission of coincidence signal. When the coincidence signal does not exist within a fixed time, a control circuit 28 successively switches the switch elements 31, then divides the source voltage by a resistance array 29 and impresses it on the gate 5 through an element 31N, and accordingly successively varies the resistance value of the element 3. The reset signals are inputted 23 into a count circuit 21 at every fixed time, and thus the detecting operation 19 is repeated. The corrected resistance 3 is connected to the fixed circuit of the LSI via terminals 18.

3. 发明专利

JPS6074559A GENERATOR FOR REFERENCE VOLTAGE 失效
公开(公告)号：JPS6074559A
公开(公告)日：1985-04-26
申请号：JP18037883
申请日：1983-09-30
申请人： HITACHI LTD , HITACHI HARAMACHI DENSHI KOGYO
发明人： OOZEKI SHIYOUICHI , URUNO TOSHIO , MIYAGAWA NOBUAKI , IKEDA TAKAHIDE , KAMEI TATSUYA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/088 , H01L27/092
摘要： PURPOSE:To set arbitrary output voltage by utilizing a difference betwen the threshold voltage of two MOS transistors and arbitrarily setting drain currents and gate length. CONSTITUTION:The titled generator is constituted by an N gate MOS transistor, in which phosphorus is doped to a gate layer in high concentration, an N region, in which the same N-type impurity phosphorus as a substrate is doped to the gate layer in low concentration, and an N gate MOS transistor in which impurity boron of the same type as source-drain is doped so as to surround the N region. When a difference between the drain voltage VN , VN of MOSFETs TN , TN having mutual conductance beta approximately equal to different threshold voltage VTHN , VTHN is taken, a difference between threshold voltage can be extracted. When drain currents or gate length is made large, the difference between threshold voltage is reduced. Gate length is set at an artibrary value, and currents from a constant current source IO are set at an arbitrary value and arbitrary output voltage cn abe obtained.

4. 发明专利

JPS58171856A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS58171856A
公开(公告)日：1983-10-08
申请号：JP5391982
申请日：1982-04-02
申请人： HITACHI LTD , HITACHI HARAMACHI DENSHI KOGYO
发明人： SHIRASAWA TOSHIKATSU , TAKAHASHI SHIGERU , TSUKUDA KIYOSHI , URUNO TOSHIO , HOSOKAWA YOSHIKAZU
IPC分类号： H03K17/73 , H01L21/331 , H01L29/08 , H01L29/73 , H01L29/74
摘要： PURPOSE:To reduce the collector resistance of a transistor and thus change it into high dv/dt strength by a method wherein a low resistance layer of resistivity lower than that of the single crystal Si region in an inductor isolation substrate and of the same conductivity type, and a transistor is formed in this low resistance layer. CONSTITUTION:The n low resistance layer 34 is formed in the n type single crystal Si region 33 which is insulation-isolated by an oxide film 32 for inductor isolation and supported by a polycrystalline Si 31, and an n collector layer 37, an n emitter layer 36, and a p-base layer 35 are formed. Further, a stabilization film 38 is laminated on the sufaces thereof, and accordingly an n-p-n transistor is constituted.

5. 发明专利

JPS60123918A REFERENCE VOLTAGE GENERATING DEVICE 失效
公开(公告)号：JPS60123918A
公开(公告)日：1985-07-02
申请号：JP23141083
申请日：1983-12-09
申请人： HITACHI LTD , HITACHI HARAMACHI DENSHI KOGYO
发明人： OOZEKI SHIYOUICHI , URUNO TOSHIO , MIYAGAWA NOBUAKI , IKEDA TAKAHIDE , KAMEI TATSUYA
IPC分类号： H03F1/30 , G05F3/24 , H01L21/822 , H01L27/04
摘要： PURPOSE:To obtain an optical output voltage, by optionally setting the drain current and gate length of an MOS transistor by utilizing the voltage difference between the gate and source of the transistor. CONSTITUTION:An optional output voltage is obtained by optionally setting the value of a constant-current source I0 by utilizing the voltage difference between the gate and source of a P-channel N gate MOS transistor and P-channel N gate MOS transistor. This output voltage is obtained by setting the gate length or drain current to an optional value.

6. 发明专利

JPS58151122A ANALOG-DIGITAL CONVERTER 失效
公开(公告)号：JPS58151122A
公开(公告)日：1983-09-08
申请号：JP3242082
申请日：1982-03-03
申请人： HITACHI LTD , HITACHI HARAMACHI DENSHI KOGYO
发明人： MIYAGAWA NOBUAKI , IKEDA TAKAHIDE , KAMEI TATSUYA , URUNO TOSHIO , YAZAWA YOSHIAKI
IPC分类号： H03M1/38 , H03M1/46
摘要： PURPOSE:To attain an A/D converter inputting an analog switch for both positive and negative polarities, by providing a register comparing an analog input voltage with a reference voltage and storing the polarity of the analog input voltage. CONSTITUTION:First, negative voltage generating circuit 100 is operated at the application of power supply, and an analog input voltage is inputted with an analog switch of a switch control circuit 101 with a signal from a control circuit 105. Then, the analog input voltage is inverted for the polarity as a positive or negative voltage. The polarity is discriminated by comparing the inputted voltage with a reference voltage (normally 0V) of a D/A converter 103 at the amplitude. The result of comparison is stored in a register 106. When the analog voltage is positive, the voltage is outputted as it is at a voltage inverting circuit 102, and when the analog input voltage is discriminated as a negative voltage, the voltage is inverted for the polarity at a voltage inverting circuit 102 while keeping the absolute value. Thus, the output voltage of the circuit 102 is always positive.

7. 发明专利

JP2754295B2 失效
公开(公告)号：JP2754295B2
公开(公告)日：1998-05-20
申请号：JP16346691
申请日：1991-06-10
申请人： HITACHI SEISAKUSHO KK , HITACHI HARAMACHI DENSHI KOGYO KK
发明人： KURITA SHINICHI , OOWADA NOBUHITO , KINASHI MASAKI , URUNO TOSHIO , SHIMURA TATSUO
IPC分类号： H01L21/02 , H01L21/336 , H01L21/76 , H01L21/762 , H01L27/12 , H01L29/739 , H01L29/74 , H01L29/78

8. 发明专利

JP2796767B2 失效
公开(公告)号：JP2796767B2
公开(公告)日：1998-09-10
申请号：JP20657492
申请日：1992-08-03
申请人： HITACHI SEISAKUSHO KK , HITACHI HARAMACHI DENSHI KOGYO KK
发明人： OOWADA NOBUHITO , KURITA SHINICHI , KINASHI MASAKI , URUNO TOSHIO , SHIMURA TATSUO , SHINNO JUJI
IPC分类号： H01L21/02 , H01L21/76 , H01L21/762 , H01L27/12

9. 发明专利

JPH0442905B2 失效
公开(公告)号：JPH0442905B2
公开(公告)日：1992-07-14
申请号：JP16457583
申请日：1983-09-07
申请人： HITACHI SEISAKUSHO KK , HITACHI HARAMACHI DENSHI KOGYO KK
发明人： MYAGAWA NOBUAKI , YAZAWA YOSHIAKI , MUKAI TOJI , IKEDA TAKAHIDE , KAMEI TATSUYA , URUNO TOSHIO , OOZEKI SHOICHI
IPC分类号： H02M7/25 , H02M3/07 , H02M7/21

10. 发明专利

JPH04196340A DIELECTRICS ISOLATION SUBSTRATE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04196340A
公开(公告)日：1992-07-16
申请号：JP32633690
申请日：1990-11-28
申请人： HITACHI LTD , HITACHI HARAMACHI SEMI CONDUCT
发明人： SUZUKI ITARU , SAKANIWA HIROTAKA , INOUE HIRONORI , URUNO TOSHIO , KURITA SHINICHI
IPC分类号： H01L21/762 , H01L21/02 , H01L21/76 , H01L27/12
摘要： PURPOSE:To eliminate the occurrence of outer peripheral polishing sag thereby avoiding the stain and separation of a wafer in the later steps by covering the peripheral part of an isolation substrate with a single crystal semiconductor. CONSTITUTION:The peripheral parts of an isolation substrate 5 are scraped off to reduce the diameter of the substrate and after bonding the substrate 5 onto the single crystal Si substrate 6 to be a supporting body, both substrate 5, 6 are joined to each other using produced silicon oxide by thermal oxidation step in oxidizing atmosphere to form a joined substrate 71. At this time, in order to bond together both substrates 5, 6, the occurrence of non-bonded part on the periphery of the contact surface 51 can be avoided by making the diameter of single crystal Si substrate 6 larger than that of the standard diameter so as to stick the isolation substrate 5 to the single crystal Si substrate 6 not through the intermediary of a bonding layer thereby making no gaps at the outer-most end of the bonding substrate 51. Through these procedures, the polishing sag can be perfectly removed thereby avoiding the separation from the wafer bonding surface 51 due to local etching step.

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